Two input bit-serial multiplier

Details Two input bit-serial multiplier Two input bit-serial multiplier

1989-12-07

1991-07-09

Shaw, Dale M.

Boots, shoes, and leggings

364758, G06F 752

Patent

active

050311379

ABSTRACT:
A reduced adder precision apparatus uses two adders to produce a serial output product of two serial input digital numbers. The multiplier operates on a bit by bit basis, beginning with the least significant bit, to determine each bit of the product without any information concerning the more significant bits. Each bit of each input is read sequentially and the bit sequences are stored in registers. A value based on the sequence built from the second digital number is added to an accumulation of a residue from a shift register used to determine the output bit of the examined bit of the first digital number is a logical one. Similarly, a value based on the sequence built from the first digital number is added to an accumulation of a residue from the shift register if the bit examined from the second digital number is a logical one.

REFERENCES:
patent: 3016195 (1954-12-01), Hamburgen
patent: 3947670 (1976-03-01), Irwin et al.
patent: 4135249 (1979-01-01), Irwin
patent: 4796219 (1989-01-01), Williams
patent: 4839847 (1989-06-01), Laprade
An O(n) Parallel Multiplier with Bit-Sequential Input and Output, Chen et al., IEE Transactions on Computers, vol. C-28, No. 10, Oct. 1979, pp. 721-727.

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