Two dimensionally addressable memory apparatus with bank switchi

Details Two dimensionally addressable memory apparatus with bank switchi Two dimensionally addressable memory apparatus with bank switchi

1985-08-16

1988-06-21

Hecker, Stuart N.

Static information storage and retrieval

Addressing

365231, G11C 700, G11C 800, G11C 802

Patent

active

047529156

ABSTRACT:
A memory apparatus is managed by two-dimensional addresses consisting of X and Y addresses and is divided into a plurality of memory banks. One of the memory banks is selected by lower significant bits including the least significant bit in each of the X and Y addresses. A different memory bank is selected by the updating of the X address or by the updating of the Y address.

REFERENCES:
patent: 3916169 (1975-10-01), Cochran et al.
patent: 4051457 (1977-09-01), Inose et al.
patent: 4074254 (1978-02-01), Belser et al.
patent: 4153950 (1979-05-01), Nosowicz et al.
patent: 4410965 (1983-10-01), Moore
patent: 4585220 (1986-04-01), Zemke et al.

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