Computer graphics processing and selective visual display system – Display driving control circuitry – Controlling the condition of display elements
Patent
1995-11-20
1997-12-09
Tung, Kee M.
Computer graphics processing and selective visual display system
Display driving control circuitry
Controlling the condition of display elements
395521, 395509, 345190, 345185, G06F 1206
Patent
active
056969473
ABSTRACT:
A two dimensional frame buffer memory interface structure is provided. The interface comprises a parallel data bus, a control signal bus, a data cache, and a controller. The parallel data bus transfers a set of pixel data in parallel to the data cache. The control signal bus transfers to the controller a X strobe signal, a Y strobe signal, and a mode signal indicating an interface mode specifying a designated pattern for the pixel data transferred over the parallel data bus. The data cache, controlled by the controller and connected to the parallel data bus, compiles each set of pixel data received over the parallel data bus into the designated pattern of pixels, as indicated by the mode signal. The controller transfers each set of pixel data from the data cache to a two dimensional frame buffer to be stored in the designated pattern at a calculated address, wherein an address in the two dimensional frame buffer is specified by an X address and a Y address and wherein the calculated address for a given set of pixel data is an X address equal to the X address of a previous set of pixel data plus, when a X strobe signal is received for the given set of pixel data, an X increment associated with the indicated interface mode, and a Y address equal to a Y address of the previous set of pixel data plus, when a Y strobe signal is received for the given set of pixel data, a Y increment associated with the indicated interface mode.
REFERENCES:
patent: 5185599 (1993-02-01), Doornink et al.
patent: 5239654 (1993-08-01), Ing-Simmons et al.
patent: 5343425 (1994-08-01), Saito et al.
patent: 5361370 (1994-11-01), Sprague et al.
patent: 5371517 (1994-12-01), Izzi et al.
patent: 5544306 (1996-08-01), Deering et al.
patent: 5572655 (1996-11-01), Tuljapurkar et al.
"Fast DRAMs can be swapped for SRAM caches" by Drive Bupsky Electronic Design, Jul. 22, 1993.
Johns Charles R.
Roberson John T.
Dillon Andrew J.
Emile Volel
International Business Machines - Corporation
Russell Brian F.
Tung Kee M.
LandOfFree
Two dimensional frame buffer memory interface system and method does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Two dimensional frame buffer memory interface system and method , we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Two dimensional frame buffer memory interface system and method will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1615929