Patent
1989-11-29
1991-06-04
Mintel, William
357 16, 357 22, 357 2312, 357 56, H01L 2702, H01L 29161, H01L 2980, H01L 2978
Patent
active
050218573
ABSTRACT:
A semiconductor device composed of an E-mode transistor and a D-mode transistor and utilizing a two-dimensional electron gas, comprising: a semi-insulating substrate (41); a channel layer (42); a carrier-supply layer (43); a threshold voltage adjusting layer (44); a first etching-stoppable layer (45); an ohmic-contactable layer; a second etching-stoppable layer (49); and a contact cap layer (50), these layers being epitaxially and successively formed on the substrate (41); source and drain electrodes (60-63) formed on the contact cap layer (50); a first gate electrode (66) of the E-mode transistor formed in a first recess (57E); and a second gate electrode (67) of the D-mode transistor formed in a second recess (57D); characterized in that the device further comprises a third etching-stoppable layer (47) which is formed in the ohmic-contactable layer to divide it into an upper portion layer (48) and a lower portion layer (46) thinner than the upper layer (48). In the formation of the first recess (57E), the upper portion layer (48) and the lower portion layer (46) are selectively and isotropically etched, and in the formation of the second recess (57D), the contact cap layer (50) and the upper portion layer (48) are selectively and isotropically etched.
REFERENCES:
patent: 4615102 (1986-10-01), Suzuki et al.
patent: 4635343 (1987-01-01), Kuroda
patent: 4733283 (1988-03-01), Kuroda
patent: 4742379 (1988-05-01), Yamashita et al.
Fujitsu Scientific Technical Journal, vol. 21; No. 3, Jul. 1985, pp. 370-379, Kawasaki, JP; T. Mimura et al.: High electron mobility transistors.
European Search Report--EP 89 31 2120.
Fujitsu Limited
Mintel William
Potter Roy
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