Two cycle asynchronous FIFO queue

Details Two cycle asynchronous FIFO queue Two cycle asynchronous FIFO queue

1995-10-27

1997-09-02

Wambach, Margaret Rose

Electrical pulse counters, pulse dividers, or shift registers: c

Systems

Pulse multiplication or division

H03K 2100

Patent

active

056639945

ABSTRACT:
A two-cycle asynchronous first-in/first-out (FIFO) device has a plurality of queue registers for holding data, and control cells coupled to the queue registers for controlling data transfer into and out of the registers. Each control cell includes interconnected first and second latches. The first latch receives a request-in signal from a previous control cell and in response produces an intermediate signal. The second latch receives the intermediate signal and in response supplies a request-out signal to a subsequent control cell. The control cell also has a logic circuit coupled to the queue register and first and second latches. In response to input signals, the logic circuit produces load and hold control signals to the queue register and first and second latches. The device includes two-to-four and four-to-two cycle converters that allow the two-cycle FIFO device to be used in either a two-cycle or a four-cycle environment.

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