Two clock microprocessor design with stall

Details Two clock microprocessor design with stall Two clock microprocessor design with stall

1994-02-08

1995-08-15

Heckler, Thomas M.

Boots, shoes, and leggings

364DIG2, 36492692, 3649256, 3649505, 3649344, G06F 110

Patent

active

054427754

ABSTRACT:
A circuit and method suspend the operation of a CPU of a microprocessor while a memory control unit (MCU) of the microprocessor performs certain operations for the CPU. The circuit is used to generate two internal clock signals from an external clock signal generated off-chip. The first internal clock signal is used to control the MCU and runs continuously. The second internal clock signal is used to control the CPU. During MCU operations requiring wait states, a stall circuit stalls the second internal clock to suspend the operation of the CPU and to thereby prevent CPU register values from changing. The circuit and method eliminate the need for certain data circulation logic within the CPU.

REFERENCES:
patent: 4748559 (1988-05-01), Smith et al.
patent: 5325521 (1994-06-01), Koyama et al.

Affiliated with

Also associated with

Rating

Two clock microprocessor design with stall does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Two clock microprocessor design with stall, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Two clock microprocessor design with stall will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2190450