Two bit vertically/horizontally integrated memory cell

Details Two bit vertically/horizontally integrated memory cell Two bit vertically/horizontally integrated memory cell

1985-04-19

1987-05-19

Carroll, J.

Static information storage and retrieval

Magnetic bubbles

Guide structure

357 4, 357 231, 357 235, 357 237, 357 41, 357 59, 365184, H01L 2712, H01L 2978, H01L 2904, H01L 2934

Patent

active

046672176

ABSTRACT:
A bit selectable, two bit per cell memory device using stacked or side-by-side fixed threshold and alterable threshold transistors. The alterable threshold transistors are used both as a switch to select the desired device or memory bank and also as a memory element. Selection between the code represented by the fixed threshold transistors and the code represented by the alterable threshold transistors is prescribed by block erase or block write cycles.

REFERENCES:
patent: 4258378 (1981-03-01), Wall
patent: 4385308 (1983-05-01), Uchida
patent: 4420871 (1983-12-01), Scheibe
patent: 4554570 (1985-11-01), Jstrzebski
Chen et al., "Stacked CMOS SRAM Cell", IEEE Electron Device Letters, vol. EDL-4, No. 8, (Aug. 1983) pp. 272-274.
Kawamura et al., "Three-Dimensional CMOS IC's Fabricated by Using Beam Recrystallization", IEEE Electron Device Letters, vol. EDL-4, No. 10, (Oct. 1983) pp. 366-368.
Gibbons et al., "Stacked MOSFET's in a Single Film of Laser-Recrystallized Polysilicon", IEEE Electron Device Letters, vol. EDL-3, No. 8, (Aug. 1982) pp. 191-193.

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