Static information storage and retrieval – Read only systems
Reexamination Certificate
1999-07-06
2001-07-10
Phan, Trong (Department: 2818)
Static information storage and retrieval
Read only systems
C365S104000
Reexamination Certificate
active
06259622
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to read only memories (ROMs) and more particularly, to Read Only Memories accessed utilizing current sense amplifiers.
BACKGROUND OF THE INVENTION
Read Only Memories (ROMs) have become widely utilized in integrated devices today. They are used, amongst other things, to store data and programs. As the market moves towards system on chip solutions, the need for large on-chip ROMs has increased. The area that is used by these ROMs is usually between 5% and 30% of the overall chip area and can be as much as 50% of the total device area. Thus, the smaller the ROM can be made, the cost thereof will decrease.
The data and programs are stored in the ROM in the form of groups of 1's and 0's (binary code), or bits, known as words. The words are permanently stored, can only be read from the memory, and are typically made up of multiples of 8 bits or bytes. Bits forming words are, in turn, derived from compartments of equal area formed into rows and columns of a ROM array. Each compartment has an address.
Reference is now made to
FIG. 1
which illustrates, by way of example, a 128 Kb ROM
10
in accordance with the prior art. ROM
10
comprises an array
12
containing 8 K words of 16 bits each. The bits of the words are configured as 256 rows and 512 columns within array
12
. Each bit of each word is derived from a distinct physical unit or cell
13
, equivalent to the compartments, imprinted on a silicon wafer utilizing digital Complementary Metal Oxide Semiconductor (CMOS) technology. A cell has a minimum manufacturable size for a particular process based on the components, e.g., transistors, that are required to be imprinted therein. Cells occur at the cross-section of rows or word lines
15
with column lines or bit lines
17
and are all the same dimensions (and area) for a given array
12
.
FIG. 1
shows a cell
13
A containing a bit of 1 at the intersection of word line
15
A with bit line
17
A. The location of particular cells
13
correspond to an address on the ROM array
12
.
ROM
10
further comprises an X-decoder
14
, a Y-decoder
16
, a selector
18
and a sense amplifier and output driver
20
. X-decoder
14
decodes 8 bits of an address which is the part of the address that determines the correct word line and activates one word line out of 256. The Y-decoder
16
selects a number of columns or bit-lines, corresponding to a word. In the present example, it connects one of every 32 cells
13
in the 16 groups of 32 cells
13
in the activated word line, in accordance with a supplied address. Y-decoder
16
achieves this by driving selector
18
, which is, in effect, a switch with multiple inputs. Thus, for each address the 16 bits of a word are selected.
Sense amplifier and output driver
20
then sense whether there is a current in bit-line
17
when connected, i.e., whether a transistor (not shown) exists in each addressed cell
13
(whether the bit is a 1), and outputs the sequence as 16 bit words. If there is no transistor, a zero bit is registered. The sensing amplifier
20
is connected to a logic control unit
22
which controls its operation.
Reference is now made to
FIG. 2
which is an illustration of a prior art layout of the two basic options for cell
13
, that is, both with ad without a transistor.
FIG. 3
shows an exemplary layout of four by four ROM cells
13
in an array
12
. In
FIG. 3
, transistors or non-transistors connected to word lines
15
, bit lines
17
and a ground connection
41
, are shown.
The basic cell
13
contains one transistor
24
or a non-transistor
25
which is made up of the constituent parts of a transistor but not connected to form a transistor. Transistor
24
is formed so that the word line
15
(
FIGS. 1
,
3
) is connected to its gate
30
. The drain
32
and source
33
of transistor
24
(with transistor) are connected to the bit line
17
(
FIG. 3
) and a shared ground
41
(
FIG. 3
) respectively. The equivalent areas of non-transistor
25
are likewise connected but do not conduct current.
Transistor
24
is composed of a diffusion layer
34
of width W, a polysilicon or poly layer
36
of length, L and a contact
38
overlapped by a metal-1 layer
40
. The diffusion layer
34
, where it touches with poly
30
at gate
36
, forms the active area or channel of transistor
24
and is a measure of the size of transistor
24
in terms of the current it draws. A non-transistor
25
does not have the diffusion layer
34
close to poly layer
36
. There is therefore no active area or channel under poly layer
36
in this cell
13
.
The minimum width and length, W
min
and L
min
of the transistor cell
24
is determined by the minimum allowed transistor size for a specific process. The minimum area of a cell
13
, in general, is a function of a number of factors. One of these factors is the overlap of the diffusion layer
34
over the contact width. Therefore, an increase in the width W of diffusion layer
34
may affect the area of cell
13
if it increases this overlap beyond a certain limit. Another factor influencing the minimum area of a cell,
13
is the length, L, of the poly layer
36
.
FIG. 3
, which is referred to hereinabove and illustrates an exemplary prior art layout of four by four ROM cells
13
in an array
12
, is now further referred to. The rows of memory cells
13
, comprising non-transistors
25
and transistors
24
share the same word line
15
as shown. Each transistor
24
or non-transistor
25
, of a row is shown connected to a different column or bit line
17
. When a word line
15
is activated, only those cells in that row which contain a transistor
24
will conduct current from their bit line
17
to group
41
(or to a virtual ground or to a reference). Which of the cells has a transistor
24
can be determined by sensing the currents on the bit lines
17
. The needed data is conveyed by pre-programming the location of the transistors in the array. As is illustrated, two basic cells
13
share the same contact
38
and all the contacts are connected together by the metal line of bit line
17
. The shared ground line
41
formed by the meeting of diffusion layers
34
from two transistors
24
or non-transistors
25
is connected to ground by a metal line (not shown), for example, every 16 cells in order to save space.
SUMMARY OF THE INVENTION
An object of the present invention is to provide multiple bit storage in a single cell of a ROM array.
A further object of the present invention is to provide means for sensing differences in size of ROM array operative elements or transistors in order to differentiate multiple bit sequences in a single cell of a ROM array.
There is thus provided a read only memory (ROM) which is made up of an array and a current sensing circuit. The array consists of a number of cells each adapted for storing N bits. Each cell has an operative element which is of one of 2
N
sizes. The current sensing circuit is connected to the array and senses the sizes of the operative elements of the array. The current sensing circuit thus differentiates among 2
N
sizes of operative elements to determine the values of each bit of the N bits of the cells of the ROM array. N is an integer greater than 1. Each operative element may further be a transistor.
Furthermore, the current sensing circuit is made up of a comparator, a reference cell and a bit line selector. The comparator includes a first branch and a number of second branches each of the second branches carrying a current. The first and second branches include one or more transistors connected to each other. The second branches may be only one branch.
The reference cell has a predetermined current level and is connected to the first branch of the comparator. The bit line selector is able to be connected to any number of the second branches of the comparator. Further, the first branch includes a transistor.
There is further provided a ROM array which is made up of a number of cells each of which is adapted for storing N bits. Each cell has an operative element
Fried Rafael
Shalit Tzahi
DSP Group Inc.
Needle & Rosenberg P.C.
Phan Trong
LandOfFree
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