Static information storage and retrieval – Interconnection arrangements – Magnetic
Reexamination Certificate
1999-09-24
2002-06-11
Nelms, David (Department: 2818)
Static information storage and retrieval
Interconnection arrangements
Magnetic
C365S163000
Reexamination Certificate
active
06404664
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention pertains to improvements in memory cell array layouts and designs, and more particularly to improvements in memory cell bit line structures, and still more particularly to improvements in twisted bit line structures and methods for making same.
2. Relevant Background
An electrical schematic diagram of a portion
10
of a memory array in which the bit line structure and method for making it in which the invention may be practiced is shown in FIG.
1
. As is well known, the memory array includes a number of word lines w
1
. . . w
6
, and complementary bit line pairs
b
1
,
b
2
,
b
2
,
b
3
, and so on.
Sensing amplifiers
12
,
12
′,
12
″, . . . are provided in association with each bit line pair. As is known, when noise, denoted by the arrows
14
—
14
appears across a pair of bit of lines, such as bit lines b
2
and
b
2
, the noise may be conducted to the sensing amplifier
12
′, and may erroneously be interpreted as data, lack of data, or undesirably modified data.
It is well known that by twisting bit line structures in integrated circuits, such as memory cells, or the like, noise that may be induced into the bit line structure can be effectively canceled. Various bit line layouts are shown in FIG.
2
. For example, in
FIG. 2
a
, a bit line arrangement is shown in which no twist exists within the bit line pairs. This is similar to the bit line arrangement of the memory array of FIG.
1
. In
FIG. 2
b
, a bit line arrangement is shown in which the twist is provided in a bit line pair located between two untwisted bit line pairs. This twist arrangement results in significantly better noise cancellation than the untwisted layout of
FIG. 2
a
, but does not provide perfect noise cancellation. In
FIG. 2
c
, a bit line arrangement is shown in which the twist is provided in each bit line pair, with the twist arranged in a staggered relationship with respect to each other. This bit line arrangement provides the best noise cancellation of the three examples shown in FIG.
2
.
More particularly, the physical layout of a typical bit line twist structure is shown in FIG.
3
. As shown, bit line
b
1
and
b
3
are continuous, but complementary bit lines b
2
and
b
2
are interconnected with a twist structure
18
. In order to accomplish the twist, bit lines b
2
and
b
2
are made discontinuous so that the respective ends of the bit line b
2
and bit line
b
2
can be interconnected.
Thus, a diagonal conducting trace
20
is provided between bit line b
2
on the right and bit line
b
2
on the left in a continuous pattern. All of the bit lines and the diagonal interconnect
20
are formed on a single level, for example, on a dielectric layer of an underlying substrate (not shown). In order to connect the left side of bit line
b
2
to the right side of bit line b
2
, an upper or lower level diagonal interconnect
22
is employed. The interconnect
22
is connected to the associated bit line segments of b
2
and
b
2
through vias
24
and
26
, and is formed in a vertical location separated from the bit line segments by a dielectric layer (not shown). Typically the interconnect
22
is formed above the level of the bit line traces, but, as mentioned, can be formed at a lower level.
Thus, conventionally, bit line structures are laid out on a semiconductor substrate by a number of parallel conductive traces. At pre-determined locations, the traces are formed in a discontinuous manner, with a diagonal interconnection made between the first set of the conductive traces and, on a different integrated circuit level, with a second diagonal interconnection between the second trace portions, with connections made to the traces by vias or other inter-level interconnections.
Thus, in the past, bit line construction has been accomplished by depositing a number of the conductive traces onto a semiconductor substrate, with spaced apart diagonal conductors formed between selected adjacent bit lines and with discontinuities in the respective lines that will subsequently be interconnected. After an insulating layer has been formed over the bit line structure, vias are formed through the insulating layer to the surfaces of the discontinuous bit lines. Thereafter, a diagonal conductor segment is formed to interconnect the discontinuous bit lines through the vias. Of course, the vertical order and placement of the diagonal interconnection may be varied, with the diagonal interconnection being first formed and the bit line structure being formed over an insulating layer in which are properly located vias may have been formed.
Thus, in order to construct twisted bit lines, a first bit line is typically constructed at an original level, and portions or segments of a second bitline are constructed parallel to the first bit line. However, in order for the second and bit line to be constructed without shorting to the first as it crosses thereover, an interconnection must be provided that is insulated from the first bit line. Such interconnection is generally constructed to be located either over or under the first and separated therefrom by a suitable insulation layer; typically, the interconnections of the second bit line are located at an upper level that is separated and insulated from the first bit line.
It should be noted that in the past, in the formation of the bitlines, a reticle has been used in which a number of opaque parallel line segments are formed on a glass substrate. The opaque parallel line segments may be formed, for example, of chromium or other material on the glass or other transparent substrate. The reticle is placed on or adjacent a surface of a substrate on which a photosensitive material has been deposited. Light is passed through the reticle, and is masked by the opaque line segments formed thereon but allowed to pass by the adjacent transparent line segments, to expose unmasked portions of the photosensitive material to the light. This causes a chemical change in the material that allows selected portions (for example, the light exposed portions) of the material to be removed.
However, since the typical scales patterned on wafers are comparable to the wave length of the light used in lithography equipment, the resulting pattern on the photosensitive material on the substrate therefore may have blurred or fuzzy edge definitions. When the photo sensitive material is removed during subsequent processing steps, the blurred or fuzzy edge definition may result in an inaccurate patterning, which, in turn, may result in unintended contact between adjacent memory array structures, such as the bit lines of concern herein.
To address this problem, a so-called “Levenson” reticle has been proposed in which selected portions of the glass substrate between masked elements are etched. The etched regions are, referred to as “&pgr;” regions, or “phases,” and the unetched regions are referred to as “0” regions, or “phases”. By careful selection of the “&pgr;” and “0” regions, a pattern can be produced onto a semiconductor device having known semiconductor processing layers thereon which have sharply defined edges. Since the etched portions of the reticle are lower than the unetched portions, light passing through the reticle has a smaller light path, and therefore causing interference patterns, on the photo resist or substrate being patterned. This results in significantly better integrated circuit structure formation. In fact, it has been estimated that a Levenson reticle can produce line patterns with approximately twice the resolution of that of a conventional reticle.
The process by which the bit lines are formed includes the exposure of a photo sensitive layer (not shown) that has been deposited or formed onto the surface of the substrate on which the bit lines are to be constructed. In the past, a reticle mask
30
has been provided, as shown in
FIG. 4
a
. The reticle mask includes a number of mask elements
32
formed on a surface
30
of a glass substrate
36
. The mask elements
32
may be, for exam
Brady III W. James
Le Thong
Nelms David
Skrehot Michael K.
Telecky , Jr. Frederick J.
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