Active solid-state devices (e.g. – transistors – solid-state diode – Lead frame – With structure for mounting semiconductor chip to lead frame
Reexamination Certificate
2000-04-07
2001-12-11
Flynn, Nathan (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Lead frame
With structure for mounting semiconductor chip to lead frame
C257S566000, C257S692000, C257S696000, C257S724000
Reexamination Certificate
active
06329707
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device such as a twin transistor package on which two transistor chips are mounted.
In the market of mobile communication, higher-gain, lower-noise, smaller-size, and lower-cost devices are requested, and high-performance, compact semiconductor devices are accordingly required. To meet this demand, twin transistor packages in which the packaging area and the number of packaging steps are reduced have conventionally been merchandized.
FIG. 9
shows the arrangement of components in a conventional twin transistor package.
Each of transistor chips (transistor pellets) Q
11
and Q
12
has a collector electrode on its lower surface and a base electrode and emitter electrode on its upper surface. The base electrode of the transistor chip Q
11
and the inner lead portion of a base lead
31
are connected to each other through a base bonding wire
41
. The emitter electrode of the transistor chip Q
11
and the inner lead portion of an emitter lead
33
are connected to each other through an emitter bonding wire
42
.
The base electrode of the transistor chip Q
12
and the inner lead portion of a base lead
35
are connected to each other through a base bonding wire
44
. The emitter electrode of the transistor chip Q
12
and the inner lead portion of an emitter lead
37
are connected to each other through an emitter bonding wire
45
. The inner lead portions of collector leads
32
and
36
respectively serve also as die pads
34
and
38
for placing the transistor chips Q
11
and Q
12
thereon.
In the twin transistor package described above, the gain and transition frequency of the transistor chip Q
11
decrease. This is because since the base lead
31
of the transistor chip Q
11
and the collector lead
32
are adjacent to each other, isolation between them is poor, and the collector-base capacitance becomes, e.g., about 80 fF.
Also, since the inner lead portion of the emitter lead
33
has a small bondable area, the emitter bonding wire
42
can be provided only one, and the emitter inductance of the transistor chip Q
11
accordingly increases. The gain and transition frequency of the transistor chip Q
12
also decrease from the same reason.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a semiconductor device in which the gain and transition frequency of incorporated transistor chips can be improved.
In order to achieve the above object, according to the present invention, there is provided a semiconductor device comprising a first transistor chip, a first base lead, first collector lead, and first emitter lead respectively having inner lead portions connected to the first transistor chip, the inner lead portion of the first emitter lead being arranged between the inner lead portion of the first base lead and the inner lead portion of the first collector lead, a second transistor chip, and a second base lead, second collector lead, and second emitter lead respectively having inner lead portions connected to the second transistor chip, the inner lead portion of the second emitter lead being arranged between the inner lead portion of the second base lead and the inner lead portion of the second collector lead.
REFERENCES:
patent: 5075759 (1991-12-01), Moline
patent: 06310662-A (1994-11-01), None
Flynn Nathan
NEC Corporation
Sughrue Mion Zinn Macpeak & Seas, PLLC
Wilson Scott R
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