Twin MONOS memory cell usage for wide program

Details Twin MONOS memory cell usage for wide program Twin MONOS memory cell usage for wide program

2002-03-15

2002-10-01

Lam, David (Department: 2818)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185030

Reexamination Certificate

active

06459622

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of Invention.
This invention relates to nonvolatile memory storage and in particular to MONOS memory.
2. Description of related art.
The twin MONOS memory cell was recently introduced in U.S. Pat. No. 6,255,166B1 (Ogura et al), directed to a nonvolatile memory cell and memory array with a method of programming the same, U.S. Pat. No. 6,248,633B1 (Ogura et al.), directed to process for making, programming and operating a dual bit multi level ballistic MONOS memory”, U.S. patent application Ser. No. 09/595,059, dated Mar. 19, 2001, directed to nonvolatile memory cell and memory array, and the operating method of the same, and U.S. Patent Application Ser. No. 10/005,932, dated Dec. 5, 2001, directed to array architecture of nonvolatile memory and operation methods.
FIGS. 1A and 1B
show schematics of two examples for the MONOS type of memory cell.
FIG. 1A
shows a diffusion bit arrangement and
FIG. 1B
shows a metal bit arrangement. In either type of memory array, bit lines vertically connect the bit diffusions of the memory cell, and are separated by three transistors in series: one control gate memory transistor, one word gate select transistor, and another control gate memory transistor. Word gates act as memory cell selectors and are shared between adjacent memory cells. The word gates are connected horizontally by word lines. Control gates have an underlying oxy-nitride-oxide (ONO) film in which it is possible to trap-electrons to store data. One control gate can trap electrons in two separate sites, and is represented by two separated transistors, the gates of which may be either physically or electrically connected together to share the same-control gate voltage.
A cross section of one word line is shown in FIG.
2
. Within a single memory cell, CELL
1
, there is a control gate CG
1
, and a bit diffusion BL
1
, as well as two half word gates. Underneath the control gate CG
1
there are two memory nitride storage sites (NSS) M
2
and M
3
. Electrons are injected into the storage sites to increase the threshold voltage of the device containing M
2
and M
3
, and by doing such, program the storage site. The injection mechanism for the twin MONOS cell is called ballistic channel hot electron (CHE), since the nitride-storage site and the channel region underneath are very short. Electron injection efficiency is very high, on the order of 1E-4, because the short channel allows less energy attenuation by electron to electron scattering. More conventional planar floating gate devices using CHE have injection efficiencies on the order of 1E-6 to 1E-10. High voltages are required during program. These high voltages are provided by charge pump circuits. Conventional devices using CHE are characterized by high program currents in the order of 100 uA/cell and program times that are often in the tens and hundreds of microseconds. The number of cells that can be programmed at once is limited; therefore, the number of cells is limited by the charge pump maximum current.
In order to erase, which decreases the threshold of a memory cell CELL
1
, a high electric field is applied between the control gate CG
1
and the bit diffusion BL
1
in order to induce either Fowler-Nordheim tunneling or Hot Hole injection, or a combination thereof, through the oxide between the nitride and the diffusion. In one such implementation, a negative voltage of approximately −2V is applied to the control gate CG
1
, and a positive high voltage of approximately 4V is applied to the bit diffusion BL
1
. In the memory array organizations shown in
FIG. 1
, there are two nitride storage sites M
2
and M
3
, which share the same control gate CG
1
and the same bit diffusion BL
1
that are usually erased together in one operation.
In the program operation however, the two nitride storage sites, which share the same control gate and the same bit diffusion may be programmed independently of each other. An example of program conditions for a twin MONOS memory array cross section are given in FIG.
3
. In order to program the selected right nitride storage site M
3
, of the selected memory CELL
1
, the control gate CG
1
is raised to +5V. The voltage of bit diffusion BL
1
is determined by the program data. Usually the bit line is connected to a program data latch. The diffusion BL
1
is raised to +5V if the cell is to be programmed to a logical “0”. Otherwise if the program data is a logical “
1
” the voltage of BL
1
is 0V. The adjacent right side bit line BL
2
is grounded. When the word line voltage is raised to a voltage of approximately 1.2V, the channel under the word gate is opened and electrons are injected from the channel into the nitride of the selected storage site M
3
. In order to inhibit programming of the left side storage site M
2
within the same memory cell CELL
1
, the left adjacent bit line BL
0
and the adjacent left control gate CG
0
are grounded to prevent current from flowing between BL
0
and BL
1
, when the threshold of the M
1
storage site is greater than zero.
However, even a small current between BL
0
and BL
1
can cause a serious program disturb condition. For that reason, if there is any possibility that the M
1
storage site is an over erased cell with a negative threshold, it is better that the voltage on BL
0
be raised to the word gate voltage, approximately 1.2V, in order to shut down the BL
0
to BL
1
current by the word gate device.
During programming, the two control gates CG[N] and CG[N+1] are raised to 3V and 5V, respectively, in order to program one of the nitride storage sites in a memory cell. To isolate programming to only one selected nitride storage site, the adjacent control gates CG[N−1] and CG[N+2] must be grounded, As illustrated in prior implementations of twin MONOS memory arrays, the minimum control gate decode is for four cells. The minimum bit line decode unit is also four cells, and the adjacent bit line next to the selected cell may need to be raised to hear the word line voltage in order to protect against an over-erased cell current during program.
FIG. 4
gives an example of voltage conditions for memory cell CELL
1
during erase. A negative voltage of around −2V is, applied to the control gate CG
1
and a positive voltage of around 5V is applied to the bit line BL
1
. Electrons are ejected from the nitride storage layer to the bit line. U.S. patent application Ser. No. 10/005,932, date Dec. 5, 2001, is directed to other possible erase mechanisms such as hot hole erase combined with word line voltage assistance. By biasing the selected word line to a negative voltage and the other word lines to a positive voltage, erase can be accelerated for the selected word line and inhibited for the unselected lines. Thus, it becomes possible to selectively erase data increments as small as a byte or even a single memory cell.
A characteristic of the short channel nitride storage region, which is implemented in the twin MONOS cell, is that program efficiency and erase efficiency can be very high.
SUMMARY OF THE INVENTION
It is an objective of the present invention to simultaneously select two nitride storage sites contained within a MONOS memory cell, for read, program and erase operations.
It is an objective of the present invention to program nitride storage sites contained within a MONOS memory cell.
It is further an objective of the present invention to program the plurality of nitride storage sites contained within a MONOS memory cell simultaneously.
It is still further an objective of the present invention to use the bit line capacitance to provide charge for a program operation.
It is another objective of the present invention to use bit line selector gates as a source follower to control the memory cell drain voltage and reduce the required bit line capacitance needed to supply current for programming cells of a memory site.
It is still another objective of the present invention to use bit line selector gates to select sub-bit lines to reduce

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