Semiconductor device manufacturing: process – Forming bipolar transistor by formation or alteration of... – Having multiple emitter or collector structure
Reexamination Certificate
1999-12-22
2001-05-08
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Forming bipolar transistor by formation or alteration of...
Having multiple emitter or collector structure
Reexamination Certificate
active
06228732
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to integrated circuits and, in particular, to a method for improving the current gain and stability of a vertical bipolar transistor structure by depositing a nitrided layer as a tunnel insulator between the transistor's monocrystalline silicon base and polycrystalline silicon emitter.
BACKGROUND OF THE INVENTION
Vertical bipolar junction transistors are widely used by the semiconductor industry as devices in integrated circuit architectures. As is well-known in the semiconductor industry, the electrical characteristics of such transistors are influenced strongly by a layer of an interfacial tunnel insulator interposed between a base region formed in a monocrystalline silicon substrate and an extrinsic emitter region of polycrystalline silicon (polysilicon) deposited thereon. Because the interfacial tunnel insulator limits reverse injection of majority carriers across the reverse biased base-emitter junction, the base current of the transistor will be minimized. The reduction in the operative base current concomitantly increases the current gain of the transistor.
The presence of a tunnel insulator can increase the current gain by a factor of about two to three. However, current gain will be maximized only by an optimal thickness of tunnel insulator. If the tunnel insulator is overly-thick, the tunneling of minority carriers is limited. As a result, the effective resistance of the emitter-base junction exceeds a desirable value. If the tunnel insulator is overly-thin, the reverse injection of majority carriers is not reduced from the base region to the emitter region. As a result, any potential benefit from the presence of the tunnel insulator is unrealized.
Conventional fabrication techniques for vertical bipolar junction transistors rely upon an interfacial layer of oxide (SiO
2
) as the tunnel insulator. Typically, the layer of oxide is composed of a native oxide. Native oxide grows naturally and spontaneously upon an unpassivated surface of a silicon substrate while that surface is exposed to the ambient oxygen content of the atmosphere. Typically, the layer of native oxide attains a thickness of between about 1 nm and about 5 nm.
A major disadvantage of relying upon native oxide as the tunnel insulator is that its nominal thickness is difficult to controllably reproduce.
Although the ultimate thickness is diffusion-limited, the nominal thickness of native oxide increases with lengthening exposure to the oxygen-laden atmosphere. Due to variable, indefinite time delays between processing steps, the thickness of the native oxide can widely vary for a single batch of silicon substrates or between successive batches. Therefore, batch fabrication may yield transistors having a wide range of current gains.
Device designs are engineered to accommodate the variation since elimination of the interfacial tunnel oxide drastically reduces the current gain of the transistor. However, the prior art has neither disclosed nor taught a method for controlling the thickness of the tunnel insulator. Simplistically, the thickness may be controlled by tightly managing the interval between successive fabrication steps and using automated mechanical loaders. In a manufacturing environment, however, mere temporal control is considered an impractical and inefficient solution.
Thus, what is ideally desired is a reproducible and predictable method of providing a tunnel insulator to enhance the current gain of a vertical bipolar junction transistor having a polysilicon emitter.
SUMMARY OF THE INVENTION
The present invention addresses these and other problems associated with the prior art by defining a method of enhancing the electrical characteristics of a vertical bipolar junction transistor. Further, the present invention provides a method of controllably forming a reproducible thickness of a tunnel insulator on the monocrystalline silicon substrate above the transistor's base region before the superjacent of the polysilicon emitter. Thus, the present invention has an advantage of substantially increasing the predictability of transistor characteristics. The present invention has yet a further advantage that device designs no longer have to be tailored to accommodate the variations in native oxide thickness and concomitant variations in current gain and emitter resistance.
According to the principles of the present invention and according to the described embodiments, the present invention is directed to a method of fabricating a vertical bipolar junction transistor that incorporates a thin layer of silicon nitride as the tunnel insulator. A method having features of the present invention comprises forming an interfacial layer by nitridation of the surface of the monocrystalline silicon substrate before depositing the transistor's polysilicon extrinsic emitter.
In one embodiment of the invention, the tunnel insulator of silicon nitride is formed by plasma-assisted thermal nitridation. Monocrystalline silicon substrates are exposed to a nitrogenous plasma generated in a reaction chamber from a partial pressure of a nitrogen-containing source gas, such as nitrogen, ammonia, a mixture of ammonia and nitrogen, or a mixture of nitrogen and hydrogen. Since the growth kinetics for a given reaction chamber can be empirically predicted, a predetermined thickness of silicon nitride can be reproducibly grown on the silicon substrate. In one aspect of the present invention, the ubiquitous layer of native oxide is removed before plasma-assisted thermal nitridation using an in-situ hydrogen plasma.
In one aspect of the first embodiment of the invention, plasma-assisted thermal nitridation is performed without first removing the native oxide layer. Nitrogen diffuses through the native oxide layer to form a thin layer of silicon nitride on the surface of the monocrystalline silicon substrate. Any residual oxide can be removed following plasma-assisted thermal nitridation using an etchant containing a given concentration of diluted hydrofluoric acid. Alternatively, the mixed oxide
itride layer can be left intact since such composite films are known to have properties desirable in a tunnel insulator.
In a second embodiment of the invention, the tunnel insulator of silicon nitride can be formed by thermal nitridation, as for example, in a furnace evacuated and backfilled with a nitrogen-rich gas. Alternatively, rapid thermal processing, as is well known in the art, provides a short-time, high-temperature method of thermal nitridation capable of forming a layer of silicon nitride without the attendant problems of dopant diffusion.
Since the growth kinetics of silicon nitride are predictable, the thickness of the tunnel insulator can be discretely engineered to achieve a particular current gain for a given transistor design. Following formation, the layer of silicon nitride acts as a diffusion barrier to prevent further oxidation of the monocrystalline silicon substrate and thickening of the layer of tunnel insulator. Because of the tightened control and stability, transistor characteristics are more uniform and reproducible during the batch processing of a plurality of monocrystalline substrates in a device fabrication line.
These and other objectives, advantages, features, and embodiments will be apparent with reference to the following drawings and detailed written description.
REFERENCES:
patent: 4755487 (1988-07-01), Scovell et al.
patent: 5585292 (1996-12-01), Morita et al.
patent: 6060403 (2000-05-01), Yasuda et al.
Takahi Ito, Tetsuo Nakamura, & Hajime Ishikawa,Advantages of Thermal Nitride and Nitroxide Gate Films in VLSI Process, IEEE Transactions On Electron Devices, vol. ED-29, No. 4, Apr. 1982, pp. 498-502.
William F. Richardson,The Fabrication and Evaluation of a Silicon Photovoltaic Cell with a Directly Nitrided Tunnel Insulator, A Dissertation Presented to the Faculty of the Graduate School University of Missouri-Columbia, May 1981.
M. Hirayama, T. Matsukawa, H. Arima, Y. Ohno, & H, Nakata, Growth Mechanism of Silicon Plasma Anode Ni
Duong AnhKim
Richardson William F.
Hoang Quoc
Nelms David
Sony Corporation
Wood Herron & Evans L.L.P.
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