Tuning of a process control based upon layer dependencies

Details Tuning of a process control based upon layer dependencies Tuning of a process control based upon layer dependencies

2002-11-25

2004-11-23

Voeltz, Emanuel Todd (Department: 2121)

Data processing: generic control systems or specific application

Specific application, apparatus or process

Product assembly or manufacturing

C438S005000, C438S014000

Reexamination Certificate

active

06823231

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to semiconductor manufacturing, and, more particularly, to a method and apparatus for selectively processing layers of a semiconductor wafer based upon layer dependencies.
2. Description of the Related Art
The technology explosion in the manufacturing industry has resulted in many new and innovative manufacturing processes. Today's manufacturing processes, particularly semiconductor manufacturing processes, call for a large number of important steps. These process steps are usually vital, and therefore, require a number of inputs that are generally fine-tuned to maintain proper manufacturing control.
The manufacture of semiconductor devices requires a number of discrete process steps to create a packaged semiconductor device from raw semiconductor material. The various processes, from the initial growth of the semiconductor material, the slicing of the semiconductor crystal into individual wafers, the fabrication stages (etching, doping, ion implanting, or the like), to the packaging and final testing of the completed device, are so different from one another and specialized that the processes may be performed in different manufacturing locations that contain different control schemes.
Generally, a set of processing steps is performed across a group of semiconductor wafers, sometimes referred to as a lot. For example, a process layer that may be composed of a variety of different materials may be formed across a semiconductor wafer. Thereafter, a patterned layer of photoresist may be formed across the process layer using known photolithography techniques. Typically, an etch process is then performed across the process layer using the patterned layer of photoresist as a mask. This etching process results in the formation of various features or objects in the process layer. Such features may be used as, for example, a gate electrode structure for transistors. Many times, trench isolation structures are also formed across the substrate of the semiconductor wafer to isolate electrical areas across a semiconductor wafer. One example of an isolation structure that can be used is a shallow trench isolation (STI) structure.
The manufacturing tools within a semiconductor manufacturing facility typically communicate with a manufacturing framework or a network of processing modules. Each manufacturing tool is generally connected to an equipment interface. The equipment interface is connected to a machine interface to which a manufacturing network is connected, thereby facilitating communications between the manufacturing tool and the manufacturing framework. The machine interface can generally be part of an advanced process control (APC) system. The APC system initiates a control application, which can be a software program that automatically retrieves the data needed to execute a manufacturing process.
FIG. 1
illustrates a typical semiconductor wafer
105
. The semiconductor wafer
105
typically includes a plurality of individual semiconductor die
103
arranged in a grid
150
. Using known photolithography processes and equipment, a patterned layer of photoresist may be formed across one or more process layers that are to be patterned. As part of the photolithography process, an exposure process is typically performed by a stepper on multiple die
103
locations at a time, depending on the specific photomask employed. The patterned photoresist layer can be used as a mask during etching processes, wet or dry, performed on the underlying layer or layers of material, e.g., a layer of polysilicon, metal, or insulating material, to transfer the desired pattern to the underlying layer. The patterned layer of photoresist is comprised of a plurality of features, e.g., line-type features or opening-type features that are to be replicated in an underlying process layer.
Turning now to
FIG. 2
, a typical flow of processes performed on a semiconductor wafer
105
by a semiconductor manufacturing system is illustrated. A manufacturing system processes semiconductor wafers
105
from a batch/lot (block
210
). Upon processing semiconductor wafers
105
, the manufacturing system may acquire metrology data relating to the processed semiconductor wafers
105
(block
220
). Based upon the analysis of the metrology data, the manufacturing system may determine one or more process control modifications that may be implemented on subsequent processes performed on the semiconductor wafers
105
(block
230
). The manufacturing system may then process subsequent semiconductor wafers
105
based upon the process modifications calculated (block
240
). The process modification may include modifying several features on a layer on the wafer
105
that may result in overlay misalignment of the layer relative to other layers on the semiconductor wafers
105
.
One problem associated with the current methodology includes the fact that a modification made upon a target layer (i.e., a layer targeted for process control modifications) may cause adverse affects on subsequent layers formed on the semiconductor wafers
105
. For example, process modifications may be made to a particular feature on a target layer, resulting in a change in the alignment of the feature relative to the alignment of corresponding features on subsequently formed layers. In the context of a photolithography process, control adjustments performed on one layer may adversely affect a plurality of other layers due to a shift in the alignment of features on various layers of the semiconductor wafers
105
. Generally, process control adjustments are made to features on layers on a wafer
105
based upon control adjustments calculated for. improvements in accuracy when processing semiconductor wafers
105
. However, utilizing the current methodology, corrections made to one layer may cause misalignment problems such that the overall accuracy and reliability of the semiconductor wafer
105
may be compromised.
The present invention is directed to overcoming, or at least reducing, the effects of, one or more of the problems set forth above.
SUMMARY OF THE INVENTION
In one aspect of the present invention, a method is provided for selectively processing a layer of a workpiece based upon dependencies with other layers in the workpiece. A process step upon a workpiece is performed. Metrology data relating to the workpiece is acquired. A process adjustment relating to a first layer on the workpiece is calculated based upon the metrology data. A determination whether an error on a second layer on the workpiece would occur in response to an implementation of the process adjustment performed on the first layer. A magnitude of the calculated process adjustment is reduced in response to a determination that the second layer would be affected in response to the implementation of the process adjustment.
In another aspect of the present invention, a system is provided for selectively processing a layer of a workpiece based upon dependencies with other layers in the workpiece. The system includes a processing tool to process a workpiece. The system also includes a process controller operatively coupled to the processing tool. The process controller is capable of performing a control tuning function. The control tuning function includes calculating a process adjustment relating to a first layer on the workpiece based upon metrology data. The control tuning function also includes reducing a magnitude of the calculated process adjustment in response to a determination that an overlay misalignment of the first and the subsequent layer would occur in response to an implementation of the calculated process adjustment upon the first layer.
In another aspect of the present invention, an apparatus is provided for selectively processing a layer of a workpiece based upon dependencies with other layers in the workpiece. The apparatus includes a process controller adapted to perform a control tuning function for processing a workpiece. The control tuning function includes calculating a

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