Amplifiers – With amplifier bypass means
Reexamination Certificate
2003-02-26
2004-08-03
Choe, Henry (Department: 2817)
Amplifiers
With amplifier bypass means
C330S149000
Reexamination Certificate
active
06771125
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to signal processing, and, in particular, to techniques for tuning amplifiers that employ feed-forward compensation.
BACKGROUND OF THE INVENTION
Amplifiers, such as high-power amplifiers used in the base stations of wireless communication systems, typically exhibit non-linearity over their operating ranges. This non-linearity can result in noise that can corrupt or otherwise interfere with the communications. To address this problem, additional circuitry may be added to an amplifier in an attempt to linearize the effective amplifier response. Conventional techniques for linearizing amplifiers typically involve pre-compensation and/or feed-forward compensation.
In amplifier linearization based on pre-compensation, the input signal that is to be amplified is pre-distorted prior to being applied to the amplifier in order to adjust the input signal based on known non-linearities in the amplifier transfer function. In feed-forward compensation, an error signal is fed forward and combined with the output of the amplifier to adjust the output signal for non-linearities in the amplifier transfer function.
FIG. 1
shows a high-level block diagram of a linearized amplifier circuit
100
according to the prior art. Amplifier circuit
100
utilizes feed-forward compensation to linearize the response of a high-power amplifier (HPA)
108
. Amplifier circuit
100
has a main amplifying chain and an error amplifier chain. The main amplifying chain includes adjuster
102
, HPA
108
, tap
110
, delay module
112
, and coupler
114
, while the error amplifier chain includes delay module
122
, coupler
124
, adjuster
130
, and error amplifier (EA)
132
. In addition, amplifier circuit
100
includes splitter
120
, pilot generator
104
, coupler
106
, taps
116
and
126
, and detectors
118
and
128
. Depending on the application, adjusters
102
and
130
may typically be implemented using vector modulators.
In operation, an input signal is split at splitter
120
and applied to both adjuster
102
and delay module
122
. In the main amplifying chain, the amplitude and/or phase of the signal from splitter
120
are (optionally) adjusted prior to being applied to HPA
108
. If pilot generator
104
is activated, then a pilot signal is injected into the signal at coupler
106
prior to being applied to HPA
108
. A portion of the amplified signal generated by HPA
108
is tapped off at tap
110
and the rest is delayed at delay module
112
(to compensate for the timing of the corresponding portion of the error amplifier chain). A feed-forward error-compensation signal (described below) from EA
132
is added to the delayed, amplified signal from delay module
112
at coupler
114
and the resulting compensated signal is provided as the output signal from amplifier circuit
100
. Detector
118
monitors a sample of the output sample received from tap
116
.
In the error amplifier chain, the signal from splitter
120
is delayed by delay module
122
(to compensate for the timing of the corresponding portion of the main amplifying chain). At coupler
124
, the portion of the amplified signal received from tap
110
is subtracted from the delayed signal from delay module
122
to generate an error signal. Adjuster
130
(optionally) adjusts the amplitude and/or phase of the error signal prior to application to EA
132
. The amplified output from EA
132
is the feed-forward error-compensation signal that is added to the delayed, amplified signal from delay module
112
at coupler
114
to generate the output signal. Detector
128
monitors a sample of the error signal received from tap
126
prior to the error signal being applied to adjuster
130
.
As indicated in
FIG. 1
, amplifier circuit
100
has two loops: a nulling loop (i.e., Loop 1 in
FIG. 1
) and an error loop (i.e., Loop 2 in FIG.
1
). According to the prior art, amplifier circuit
100
is tuned by first tuning the nulling loop and then tuning the error loop. In particular, the nulling loop is tuned by applying an input signal to amplifier circuit
100
(with pilot generator
104
turned off) and using nulling-loop adjuster
102
to adjust the amplitude and/or phase of its applied signal until the power of the error signal detected by detector
128
is minimized. After the nulling loop has been tuned and with the input signal typically still present, the error loop is then tuned by (i) injecting a known pilot signal (e.g., one or more continuous wave (CW) signals or a spread-spectrum signal) from pilot generator
104
at coupler
106
and, (ii) with nulling-loop adjuster
102
locked to its tuned setting, using error-loop adjuster
130
to adjust the amplitude and/or phase of the signal in the error amplifier until the power of the pilot signal detected by detector
118
is minimized (e.g., ideally zero).
In order to maintain tuning of a real-world amplifier system in which operating characteristics vary over time with changes in the input signal, the ambient temperature and humidity, and the like, the system-tuning process consisting of first tuning the nulling loop followed by tuning of the error loop is typically continuously or at least periodically repeated to dynamically adjust the operations of amplifier circuit
100
.
In order for detector
118
to be able to distinguish the presence of the amplified pilot signal from the amplified input signal, the pilot signal injected at coupler
106
must be different in some way from the input signal. In some prior art implementations, pilot generator
104
is designed to generate the pilot signal as a CW signal having a frequency different from those frequencies contained in the input signal. In this case, detector
118
is typically implemented as a narrow-band detector that is able to detect the presence of the amplified CW pilot signal in the otherwise wide-band output signal.
REFERENCES:
patent: 4394624 (1983-07-01), Bauman
patent: 6091297 (2000-07-01), Bar-David et al.
patent: 6232838 (2001-05-01), Sugimoto
patent: 6531918 (2003-03-01), Posner et al.
patent: 2003/0034834 (2003-02-01), Blodgett
Andrew Corporation
Choe Henry
Mendelsohn Steve
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