Wave transmission lines and networks – Negative resistance or reactance networks of the active type – Simulating specific type of reactance
Reexamination Certificate
2002-03-15
2003-09-30
Nguyen, Patricia (Department: 2817)
Wave transmission lines and networks
Negative resistance or reactance networks of the active type
Simulating specific type of reactance
C333S217000, C333S213000
Reexamination Certificate
active
06628181
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a tuning circuit capable of increasing Q thereof up to a desired predetermined value wherein a negative resistance circuit is added to a resonance circuit comprising an inductor and an capacitor.
2. Description of the Related Art
There are methods using a negative resistance circuit as a method for increasing Q of a tuning circuit. As one of them a regeneration detection method has been many used. However, it is necessary to set up a positive feedback circuit whenever a tuning frequency is changed because the positive feedback circuit is used on the eve of oscillation and a set up value thereof is not constant.
There is an automatic setting method of a tuning frequency in order to improve this drawback, which is disclosed in Japanese Patent Application No. 2000-400944. According to said method, in such condition as to oscillate a tuning circuit weakly, a resistance component of the tuning circuit is obtained by the operation from relation between a negative resistance value and an oscillation signal amplitude when the oscillation signal amplitude is varied by scanning the negative resistance value. Since this method requires several numeric operation comprising multiplication and division, it is very complicated and it is impossible to hold operation result completely.
Further, there is a method disclosed in Japanese Patent Application No. 2001-19748 to improve this drawbacks. This method has such merits that a circuit for it can be miniaturized and it is possible to hold operation result completely because most of the circuit may be constituted to operate digitally but it has such demerit that detection accuracy of standard time (a time when the oscillation signal amplitude becomes zero) to determine operation accuracy.
SUMMARY OF THE INVENTION
An object of the invention is to provide a tuning circuit capable of setting Q thereof to a desired high predetermined value by a very simple circuit wherein this standard time can be detected simply and accurately because it is impossible to detect the standard time accurately by the method of Japanese Patent Application No. 2001-19748.
In order to achieve the above object, a tuning circuit of the invention comprises a resonance circuit consisting of an inductor and a capacitor and a negative resistance circuit connected to the resonance circuit in series;
negative resistance control means for setting a negative resistance value of the negative resistance value to make an effective resistance value of the tuning circuit to be negative so as to oscillate and for varying said negative resistance value in positive direction;
stop holding means for holding a first negative resistance value when an amplitude of an oscillation signal outputted from said resonance circuit becomes a first predetermined value and for outputting a second negative resistance value when said amplitude becomes a second predetermined value of half of the first predetermined value to stop varying of said negative resistance value; and
operating means for operating the negative resistance value of said negative resistance circuit to obtain a desired Q of the tuning circuit from said first and second negative resistance values.
In the invention, it is preferred that a negative resistance amending value corresponding to time delay of variance of the oscillation signal due to variance of the negative resistance value is applied to said operating means.
Further, in the invention, it is preferred that said negative resistance control means comprises a counter for counting clock signals to control the negative resistance value in accordance with the count output of the counter and said stop holding means comprises first and second comparators for detecting that said oscillation signal becomes the first and second predetermined values respectively and a latch circuit for holding said second negative resistance value.
Furthermore, in the invention, it is preferred that the second negative resistance value from said second comparator is shifted by one bit so as to make it be two times and is applied to said operating means.
In addition, in the invention, it is preferred to include means for disconnecting an input and an output of the tuning circuit therefrom.
REFERENCES:
patent: 4338582 (1982-07-01), Presser
patent: 5451915 (1995-09-01), Katzin et al.
patent: 5539761 (1996-07-01), Golub et al.
patent: 6239664 (2001-05-01), Northam
patent: 6504458 (2003-01-01), Kawai
patent: 6545570 (2003-04-01), Kawai
General Research of Electronics Inc.
Nguyen Patricia
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