Tuning alignment data memory device for tuning circuits tunable

Details Tuning alignment data memory device for tuning circuits tunable Tuning alignment data memory device for tuning circuits tunable

1987-04-06

1988-05-03

Griffin, Robert L.

Telecommunications

Receiver or analog modulated signal frequency converter

Signal selection based on frequency

455195, 455197, 3581911, H04B 1116, H04B 126

Patent

active

047425644

ABSTRACT:
The invention relates to a tuning memory device for tuning circuits to selectable frequencies and in which digital tuning data corresponding to said frequencies are stored in a programmable memory. For each selectable frequency the programmable memory contains an information element indicating whether writing said line has been effected correctly. A logic frequency-selection circuit includes a buffer register (REG) receiving address data from a BUS, which data are loaded in an up/down counter UP/DN, and a shift register L.sub.1 . . . L.sub.n which is clocked by a clock signal (MW,CR). Each time a defective row of the memory is detected (signal BLD), the up/down counter UPDN is decremented by one unit so a defective row is not counted. When the up/down counter reaches a predetermined count, identified by a gate 40, the shift register is positioned to the desired row corresponding to the selected frequency and addresses via the output of a corresponding register multivibrator (L.sub.1 . . . L.sub.n) a row of the programmable memory.

REFERENCES:
patent: 4361909 (1982-11-01), Theriault
patent: 4491975 (1985-01-01), Ito
patent: 4503465 (1985-03-01), Wine
patent: 4608712 (1986-08-01), Fedde
"Session V--TV Signal Processing II," Dumont et al., 1985 IEEE, pp. 78-79.

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