Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified configuration
Reexamination Certificate
1998-12-16
2001-12-11
Loke, Steven (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified configuration
C257S383000, C257S767000, C257S773000
Reexamination Certificate
active
06329720
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to an integrated circuit structure formed with a local interconnect. More particularly, this invention relates to a silicon integrated circuit structure having a tungsten local interconnect.
2. Description of the Related Art
Conventionally an integrated circuit structure may be constructed with local interconnects formed in between adjacent conductive portions of the integrated circuit devices, such as in between the source/drain electrodes of adjacent MOS transistors. Such local interconnects may be formed using the same conductive material as the filler material, e.g., tungsten, used to fill the contact openings which provide electrical connection to other portions of the integrated circuit structure.
With the shrinking of the minimum feature size of integrated circuit structures, the scaling down of the interconnect becomes important to increase the chip density. Tungsten local interconnect is a technology which allows designers of integrated circuit structures to use the first tungsten contact layer as a circuit routing layer, and thus increase the chip density and routing flexibility. However, conventional tungsten local interconnect technology does not allow the tungsten lines at the contact layer level to go across unrelated polysilicon and diffusion regions. That is, conventional tungsten local lines or “interconnects” cannot bridge over conductive regions, but can only be used to interconnect adjacent conductive regions separated by an insulator, and therefore, are conventionally referred to as “local” interconnects. This represents a significant limitation to the use of tungsten interconnect technology as a circuit routing layer.
In copending Pasch et al. U.S. patent application Ser. No. 09/081,403, filed by one of us with another on May 18, 1998, and assigned to the assignee of this invention, and the incorporation of which herein by reference is hereby made, a structure is described and claimed to overcome this problem. A plurality of dielectric layers is provided with the lowest dielectric layer formed over the underlying integrated circuit structure to a height or thickness as high as, or preferably exceeding, the height of the highest conductive regions of the underlying integrated circuit devices; a second dielectric layer is formed above the first dielectric layer with one or more local interconnects formed in this second dielectric layer; and then a thin third dielectric layer is formed over the second dielectric layer and the local interconnects therein. The first layer of metal interconnects is then formed over the thin third dielectric layer.
SUMMARY OF THE INVENTION
The invention comprises an integrated circuit structure and method of making same wherein a local interconnect may be formed, for example, from the same material used to fill contact openings, and the local interconnect is capable of bridging over a conductive element in the integrated circuit structure to electrically connect together, at the local interconnect level, non-adjacent conductive portions of the integrated circuit structure. After formation of active devices and a conductive element of an integrated circuit structure in a semiconductor substrate, a silicon oxide mask is formed over the structure, including the conductive element, with openings provided in the mask corresponding to silicon regions where metal silicide is to be formed. Metal silicide is then formed through the openings in the silicon oxide mask over and in the exposed silicon regions. At least the portion of the silicon oxide mask layer over the conductive element is then retained as insulation on the structure after the silicide formation step. A silicon nitride etch stop layer and a planarizable dielectric layer are then formed over the entire structure and planarized. One or more openings are then formed through such further layers conforming to regions where contact openings and one or more local interconnects are to be formed, including an opening in the silicon nitride and dielectric layers over the conductive element and exposed metal silicide regions adjacent the conductive element. One or more layers of conductive metal are then deposited over the entire structure to fill the contact openings and the local interconnect opening. The conductive metal is then planarized with the surface of the planarizable dielectric layer to form a local interconnect which bridges over the conductive element to electrically connect the exposed metal silicide regions adjacent the conductive element, with the portion of the silicon oxide mask retained over the conductive element providing insulation to electrically separate the local interconnect from the conductive element. A formula is also provided for calculating the thickness range of the silicon oxide mask layer when a silicon nitride etch stop layer is utilized.
A further dielectric layer is then formed and planarized over the planarizable dielectric layer with vias formed through this further dielectric layer to the filled contact openings and local interconnects in the planarizable dielectric layer. A patterned metal interconnect layer is then formed over this further dielectric layer and in registry with the filled vias in the further dielectric layer.
In another embodiment, wherein the conductive element is also silicon and the formation of metal silicide on the conductive element is also desired, e.g., to reduce the resistance of the conductive element, the metal silicide is formed prior to formation of the silicon oxide mask layer over the conductive element. The silicon oxide mask layer is then formed over the silicided conductive element, and the remainder of the process is then carried out as previously described.
REFERENCES:
patent: 5807779 (1998-09-01), Liaw
patent: 3-175676 (1991-07-01), None
Li Weidan
Rakkhit Rajat
Yeh Wen-Chin
Loke Steven
LSI Logic Corporation
Taylor, Esq. John P.
Vu Hung Kim
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