Tuner device

Details Tuner device Tuner device

1999-12-17

2003-09-23

Bost, Dwayne (Department: 2681)

Telecommunications

Receiver or analog modulated signal frequency converter

Signal selection based on frequency

C450S145000, C450S145000, C450S145000, C450S145000, C450S145000, C375S344000

Reexamination Certificate

active

06625431

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a tuner device such as a television receiver, a cable television or the like, for example, having a PLL (phase-locked-loop) tuning controller for controlling the oscillation frequency of a local oscillator.
The tuner device for a television receiver, for example, having a PLL tuning controller performs the phase lock operation at the time of the tuning operation using the PLL in a manner that the detecting operation of a synchronous signal is performed and the detecting operation of an inflection point of an AFC (automatic frequency control) voltage is performed thereby to lock the center frequency to a receiving frequency (see Japanese Patent Publication No. 2-46206A, for example).
In such a tuner device, the PLL tuning controller performs the phase lock operation in a manner that the detecting operation of the synchronous signal (hereinafter referred to an SD signal) is performed, then the detecting operation of the level inflection point of an AFC voltage (hereinafter referred to an AFC operation) is performed twice to the frequency increasing direction and the frequency decreasing direction, thereby to lock the center frequency to the receiving frequency.
The explanation will be made as to the related SD signal detection operation and AFC operation.
In the related SD signal detection operation, the PLL tuning controller outputs the frequency, that is, PLL data corresponding to the frequency of a broadcasting to be received thereby to detect the SD signal. That is, the SD signal detection is performed in a manner that the PLL tuning controller firstly outputs the signal with a frequency deviated by −1.3 MHz from the center frequency of the broadcasting to be received, then outputs the signal with a frequency deviated by −2.6 MHz from the center frequency, then outputs the signal with a frequency deviated by +1.31 MHz from the center frequency, and finally outputs the signal with the center frequency again.
If the SD signal is detected in any point, the process proceeds to the AFC operation at this time point.
FIG. 2
is a diagram showing the relationship between the SD signal as to the AFC voltage and a signal DIR for detecting the level inflection point of the AFC voltage. The SD signal has a frequency width of 1.0 to 1.2 MHz to the negative direction (frequency reducing direction) as to the center frequency (e.g., 45.75 MHz) of the intermediate frequency (IF) and has a frequency width of 0.4 to 0.7 MHz to the positive direction (frequency increasing direction) as to the center frequency, and hence has a frequency width of 1.4 to 1.9 MHz in total. The AFC voltage is converted into a digital value through the analog-to-digital (A/D) conversion in order to obtain the DIR signal. That is, for example, the AFC voltage less than 2.5 volt is converted into a low level “L” and the AFC voltage of 2.5 volt or more is converted into a high level “H”.
In the AFC operation, a level shift point of the DIR signal is searched by changing the intermediate frequency (IF) step by step in three steps totally (one step is 27.965 kHz) to each of the frequency increasing and decreasing directions. In this case, when the AFC voltage is lower than 2.5 volt (for example, a point shown by a reference numeral
81
in FIG.
2
), the PLL data is changed so as to decrease the intermediate frequency (IF) until the AFC voltage exceeds 2.5 volt. In contrast, when the AFC voltage is higher than 2.5 volt (for example, a point shown by a reference numeral
82
in FIG.
2
), the PLL data is changed so as to increase the intermediate frequency (IF) until the AFC voltage decreases less than 2.5 volt. In this manner, the first operation is performed. In the first operation, the threshold value is set to 2.5 volt.
Then, when the level shift point of the DIR signal is detected in the first operation, the PLL data is changed so as to change the intermediate frequency step by step to the reversed direction of the first operation until the AFC voltage exceeds 2.5 volt or decreases lower than 2.5 volt thereby to detect again the level shift point of the DIR signal. In this manner, the second operation is performed. In the second operation, the threshold value is set to 2.5 volt as same as the first operation.
When the level shift point of the DIR signal is again detected in the second operation, the intermediate frequency is fixed, and the SD signal detection is performed again. In this manner, a series of the tuning operation is completed. When the aforesaid operations are performed normally, the intermediate frequency can be fixed to the final tuning point
83
shown in FIG.
2
.
As described above, in the aforesaid related AFC operation, the threshold value for detecting the level shift point of the DIR signal is set to 2.5 volt as to each of the first and second operations.
However, the level of the AFC voltage sometimes changes unexpectedly irrespective of the frequency controlled by the PLL tuning controller. For example, when the actual frequency transmitted from a broadcasting is deviated from the center frequency of the broadcasting to be received based on the PLL data outputted from the PLL tuning controller (for example, when the former deviates from the latter by −0.5 MHz), the level of the AFC voltage changes unexpectedly. The reason of such a phenomenon is considered that the ripple generated within the PLL is superimposed on the output frequency thereof.
In this case, the intermediate frequency at the time where the SD signal is detected corresponds to the point
81
shown in FIG.
2
. In this state, supposing that the level of the AFC voltage varies as shown by a dashed line shown in
FIG. 2
, there arises a problem that if the first operation is started in this state, the level of the AFC voltage exceeds 2.5 volt at a point
84
shown in
FIG. 2
before the intermediate frequency reaches to the original final tuning point (frequency) and so the intermediate frequency is fixed to the deviated point
84
. In other words, there arise a problem that the receiving frequency can not be fixed accurately to the center frequency of a broadcasting to be received.
SUMMARY OF THE INVENTION
The present invention has been made in view of the aforesaid problem, it is therefore an object of the present invention is to provide a tuner device which can accurately fix a receiving frequency to the center frequency of a broadcasting thereby to terminate the tuning operation even if the level of an AFC voltage changes unexpectedly.
In order to attain the aforesaid object, there is provided a tuner device comprising:
a local oscillator; and
a phase-locked loop (PLL) tuning controller for:
monitoring a voltage value of an automatic frequency control (AFC) signal;
detecting a first frequency at which a first threshold voltage value accords with the AFC voltage value while varying an oscillation frequency of the local oscillator in either direction of frequency-increasing or frequency-decreasing in accordance with an AFC value when a synchronous signal of a broadcasting to be received is first detected;
detecting a second frequency at which a second threshold voltage value having a value different from the first threshold value accords with the AFC voltage value while varying the oscillation frequency in a reversed direction for which the first frequency has been detected; and
locking the second frequency as a center frequency of the broadcasting to be received.
The first threshold voltage value is set as two voltage values defining a predetermined voltage width, and the second threshold voltage value is set as a predetermined single voltage value.
The predetermined voltage width is set so as to cover an irregular variation width of the AFC voltage value.
When the lower value of the first threshold voltage value is set as A
1
, the higher value of the first threshold voltage value is set as A
2
, and the second threshold voltage value is set as B, the PLL tuning controller lowers the oscillation frequency until the AFC voltage value exceeds th

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