Tunable synchronous electronic communication apparatus

Details Tunable synchronous electronic communication apparatus Tunable synchronous electronic communication apparatus

1992-12-17

1995-05-09

Heckler, Thomas M.

G06F 104

Patent

active

054148324

ABSTRACT:
A synchronous communication apparatus can be tuned to ensure reliable reception of signals propagating along transmission lines. The apparatus can be used as a communication port in a high frequency, highly connected synchronous network in which all ports can be tuned by a single, remote network control device. A local data source outputs a data signal during each of a series of local clock periods. A local source delay circuit receives input data signals from the local data source, and outputs output signals delayed by all amount (mT+.DELTA.pT) relative to corresponding input data signals, where m is a positive integer or zero, and where 0<.DELTA.p<1. The amount of the delay is dependent on the value of a source delay select signal. A local data receiver receives data signals from a local receiver delay circuit. The amount of delay of the local receiver delay circuit is also selectable. A remote data signal reflection circuit has an input connected to the output of the local source delay circuit by way of a first transmission line. The remote data signal reflection circuit has an output connected to the input of the local receiver delay circuit by way of a second transmission line. The remote data signal reflection circuit outputs an acknowledge signal having a value which is dependent on the value of a corresponding data signal received by the remote data signal reflection circuit from the local data source.

REFERENCES:
patent: 3651481 (1972-03-01), Evans et al.
patent: 4063308 (1977-12-01), Collins et al.
patent: 4330846 (1982-05-01), Colles et al.
patent: 4426685 (1984-01-01), Lorentzen
patent: 4546269 (1985-10-01), Johnson
patent: 4562573 (1985-12-01), Murano et al.
patent: 4700347 (1987-10-01), Rettberg et al.
patent: 4714924 (1987-12-01), Ketzler
patent: 4881165 (1989-11-01), Sager et al.
patent: 4931986 (1990-06-01), Daniel et al.
patent: 4984255 (1991-01-01), Davis et al.
patent: 5118975 (1992-06-01), Hillis et al.
patent: 5140688 (1992-08-01), White et al.
Noakes, M., et al. "System Design of the J-Machine." Proceedings of the Sixth MIT Conference on Advanced Research in VLSI, Cambridge, Mass., Apr. 2, 1990, pp. 179-194.
Rettberg, R. D., et al. "The Monarch Parallel Processor Hardware Design." IEEE Computer, vol. 23, No. 4, Apr. 1990, pp. 18-30.

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