Tunable on-chip capacity

Details Tunable on-chip capacity Tunable on-chip capacity

2000-12-15

2003-03-18

Ham, Seungsook (Department: 2817)

Wave transmission lines and networks

Automatically controlled systems

C333S181000, C333S02400C

Reexamination Certificate

active

06535075

ABSTRACT:

TECHNICAL FIELD
The invention relates to a tunable on-chip capacity device for a semiconductor chip mounted on a substrate and including a plurality of on-chip power supply decoupling capacitors which are connected to a power supply network. The invention also relates to a method for tuning the capacity of on-chip power supply decoupling capacitors.
BACKGROUND ART
On-chip power supply decoupling capacitors are used to stabilize the on-chip power supply system of synchronously clocked CMOS chips. The highly synchronous on-chip switching activity and its associated high frequency current demand prevents to rely only on off-chip power supply decoupling capacitors. The inductive connection paths between on-chip switching circuitry and off-chip power supply decoupling capacitors do not allow to transfer high amounts of charge in a short time. The initial charge demand of an on-chip switching event has to be served first from on-chip power supply decoupling capacitors. Recharging of the on-chip decoupling capacitors from off-chip capacities happens afterwards with lower speed.
WO96/33495 discloses on-chip power supply decoupling capacitors which are directly connected to the on-chip power distribution network. The capacitors may be implemented by CMOS devices. The known circuit includes a self-repairing capability by using a cross-coupled structure which reacts to a leakage current in one of the transistors to switch into another state. Such circuit facilitates the testability of the whole chip by reducing keeping leakage currents initiated by coupling capacitors. The known on-chip power supply decoupling capacitors have fixed capacity values according to the design specifications. A late adaptation of the capacity values according to the measured chip, module or card conditions is thus prevented.
SUMMARY OF THE INVENTION
It is an object of the invention to propose an on-chip power supply decoupling capacitor arrangement for semiconductor chips which allows a reduction of the on-chip power supply voltage noise and a reduced switching power.
It is also an object of the invention to provide an integrated semiconductor chip mounted on a substrate with a tunable capacity of a plurality of on-chip power supply decoupling capacitors distributed on the chip area.
It is a further object of the invention to provide a method for tuning the capacity of a plurality of on-chip power supply decoupling capacitors according to circuit specific frequency conditions of the power supply during chip switching.
The circuitry according to the invention, as defined in the claims, comprises a set of on-chip power supply decoupling capacitors which can be selectively activated or deactivated by being switched on or off the power supply system. The on-chip capacitors are part of the packaging intrinsic power resonance loop which comprises a fixed on-module decoupling capacity, the total active on-chip capacity including parasitic on-chip capacities, and a parasitic path impedance between both. The power resonance loop is tuned according to the synchronous reaction with the periodic power supply current demand of the chip. Resonance loop tuning is accomplished by changing the capacity of the on-chip power supply decoupling capacitors by activating or deactivating more or less of the on-chip power supply decoupling capacitors. The tuning operation provides a minimum of simultaneous switching noise and a minimum operation power consumption.
According to another aspect of the invention the on-chip power supply decoupling capacitors which are selectively activated or deactivated have different capacities and the selection for activating or deactivating the capacitors may take place in an order of increasing capacity by deactivating one of a plurality of on-chip power supply decoupling capacitors and instead activating another one of that plurality.
Furthermore, according to the invention a method is provided, as defined in the claims, for tuning the capacity of on-chip power supply decoupling capacitors on a semiconductor chip mounted on a substrate by identifying oscillations of a resonance loop which includes said off-chip path impedance, an off-chip capacity and the total on-chip capacity as provided by the plurality of on-chip power supply decoupling capacitors and said parasitic on-chip capacities, and by tuning said resonance loop through changing the total capacity of said power supply decoupling capacitors.
The invention permits an adaptation of the capacity of on-chip power supply decoupling capacitors which results in a reduction of the on-chip power supply voltage noise and the required chip switching power and thus provides an improved product quality level.


REFERENCES:
patent: 3475702 (1969-10-01), Ainsworth
patent: 5117206 (1992-05-01), Imamura
patent: 5392456 (1995-02-01), Mitomo et al.
patent: 5726870 (1998-03-01), Lavieville et al.
patent: 6333674 (2001-12-01), Dao

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