Tunable gate linewidth reduction process

Details Tunable gate linewidth reduction process Tunable gate linewidth reduction process

1999-08-25

2002-03-26

Goudreau, George (Department: 1763)

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

C430S005000, C438S622000, C438S734000, C438S736000, C438S739000, C438S717000, C438S719000

Reexamination Certificate

active

06362111

ABSTRACT:

FIELD OF THE INVENTION
This invention generally relates to transistor formation and more specifically to a process for forming polysilicon gate/lines having a narrow width.
BACKGROUND OF THE INVENTION
As CMOS technology pushes deeper into the submicron region, it becomes more difficult to lithographically pattern the smaller linewidths needed. Some of the most prominent critical issues are cost, performance, and manufacturing worthiness of the lithography tool needed for patterning of device dimensions less than 0.15 &mgr;m with tight critical dimension (CD) control. I-line lithography has been reliably used in 0.50 &mgr;m and 0.35 &mgr;m CMOS production.
An alternative approach to achieving deep-submicron linewidths lithographically is resist ashing. In this approach, after a resist pattern is formed lithographically, the resist is eroded to achieve a reduction in linewidth. Resist ashing techniques have been reported to produce 0.1-0.2 &mgr;m polysilicon gate length MOS devices using conventional g-line lithography. However, this technique can not meet the stringent CD control requirements, across the wafer (e.g., <0.025 &mgr;m) and from wafer-to-wafer (e.g., 3-Sigma=0.025 &mgr;m), needed for sub-0.25 &mgr;m processing.
Another prior art approach uses a fluorine-based etch chemistry for pattern linewidth reduction. In this approach, a BARC (bottom anti-reflective coating) layer is formed over the polysilicon prior to resist coating. A pattern is formed of the resist using conventional lithography. A fluorine-based etch is then used to etch the BARC. The etch is continued past endpoint into an overetch which has a horizontal etch component that reduces the width of the remaining BARC and resist pattern. This creates a pattern having a width less than the minimum lithography tool capability. After the overetch, the wafer is transferred to a separate chamber and the reduced-width pattern is then used for the polysilicon etch. However, this approach has disadvantages, since the fluorine-based BARC etch chemistry can remove a significant amount of the polysilicon layer during the BARC overetch, making the subsequent polysilicon etch more difficult.
SUMMARY OF THE INVENTION
A process for forming a polysilicon line having linewidths below the lithography tool limits is disclosed herein. The layer of polysilicon is deposited over a semiconductor body. A layer of bottom anti-reflective coating (BARC) is deposited over the polysilicon layer. A resist pattern is formed over the BARC layer using conventional lithography (e.g., deep UV or I-line lithography). The resist pattern has minimum dimensions of the lithography tool limits or greater. The BARC layer is etched with a chemistry comprising HBr and O
2
until the endpoint is detected. The etch is continued past endpoint into an overetch portion where the etch has a horizontal component that reduces the width of both the resist and BARC layers. The minimum dimension of the pattern is reduced to below the lithography tool limits. Finally, the polysilicon layer is etched using the reduced width pattern.
An advantage of the invention is providing a process for controllably forming polysilicon lines having a minimum dimension less than the practical resolution limits of the lithography tool (e.g., less than 0.18 &mgr;m for deep UV lithography).
This and other advantages will be apparent to those of ordinary skill in the art having reference to the specification in conjunction with the drawings.


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