Electricity: electrical systems and devices – Safety and protection of systems and devices – Load shunting by fault responsive means
Reexamination Certificate
2006-11-14
2006-11-14
Sircus, Brian (Department: 2836)
Electricity: electrical systems and devices
Safety and protection of systems and devices
Load shunting by fault responsive means
C257S362000
Reexamination Certificate
active
07136268
ABSTRACT:
A circuit and a method for the electrostatic discharge protection of integrated circuits. The electrostatic discharge protection circuit, including: an electrostatic discharge protection circuit, comprising: a first bipolar transistor coupled between a first circuit node and a second circuit node, the first bipolar transistor having a non-uniform subcollector region geometry, the first bipolar transistor having a different value for collector to emitter breakdown voltage than a value for collector to emitter breakdown voltage of an otherwise identical bipolar transistor having a uniform subcollector region geometry.
REFERENCES:
patent: 6552406 (2003-04-01), Voldman
patent: 6720637 (2004-04-01), Voldman
patent: 6878976 (2005-04-01), Coolbaugh et al.
patent: 7001806 (2006-02-01), Tilke et al.
patent: 7012288 (2006-03-01), Lee et al.
Sue E. Strang et al., A Design System for Auto-Generation of ESD Circuits, Sep. 16-18, 2002, IBM Communications Research and Development Center (CRDC), 10 pages.
Stricker Andreas D.
Voldman Steven H.
Benenson Boris
Canale Anthony
International Business Machines - Corporation
Schmeiser Olsen & Watts
Sircus Brian
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