TTL to CMOS logic level translator

Details TTL to CMOS logic level translator TTL to CMOS logic level translator

1989-03-07

1990-04-10

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307451, 307479, 307585, 323316, 330288, H03K 19092, H03K 19094, H03K 1920, H03K 1704

Patent

active

049163370

ABSTRACT:
Four transistors, a pair of buffers, and an inverter are configured with the first transistor connected in a pull-up configuration, with the transistor drain connected to a first node and with the transistor gate connected to a second node. The second transistor is connected in a pull-down configuration, with the transistor gate connected to a (data) input line and with the transistor drain connected to the first node. The third transistor is also connected in the pull-up configuration, with the transistor gate connected to the first node and with the transistor drain connected to the second node. The fourth transistor is also connected in the pull-down configuration, with the transistor gate coupled by the inverter to the input line and with the transistor drain connected to the second node. The buffers are each connected between a respective one of the nodes and a respective one of two (data) output lines.

REFERENCES:
patent: 4380710 (1983-04-01), Cohen et al.
patent: 4677321 (1987-06-01), Bacrania
patent: 4682047 (1987-07-01), Sichart
patent: 4686383 (1987-08-01), Croft
patent: 4717845 (1988-01-01), Dunn
patent: 4763022 (1988-08-01), Sheldon
patent: 4845388 (1989-07-01), Amatangelo

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