TTL to CMOS input buffer using CMOS structure

Details TTL to CMOS input buffer using CMOS structure TTL to CMOS input buffer using CMOS structure

1991-09-26

1993-12-07

Westin, Edward P.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307451, 307446, 3072968, H03K 19092, H03K 19094

Patent

active

052685993

ABSTRACT:
The present invention provides a buffer circuit, which comprises a CMOS logic gate circuit in which at least one gate input terminal is input from other circuit, a MOS transistor for controlling a threshold voltage, which is inserted in series into a current path between power source electrodes of the CMOS logic gate circuit including MOS transistors connected to the input terminal, and a control circuit for controlling a gate voltage of the MOS transistor for controlling the threshold voltage such that the logic threshold voltage in the input terminal coincides with a predetermined logic threshold voltage without depending on variation in a power supply voltage, temperature, or a manufacturing process. The logic threshold voltage of the buffer circuit can be maintained constantly without depending on variation in the power supply voltage or temperature.

REFERENCES:
patent: 4642488 (1987-02-01), Parker
patent: 5010259 (1991-04-01), Inoue et al.
patent: 5021685 (1991-06-01), Kihara
patent: 5073726 (1991-12-01), Kato et al.

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