TTL to CMOS input buffer circuit for minimizing power consumptio

Details TTL to CMOS input buffer circuit for minimizing power consumptio TTL to CMOS input buffer circuit for minimizing power consumptio

1984-01-12

1986-04-22

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307443, 307451, 307579, H03K 19094

Patent

active

045844917

ABSTRACT:
A buffer circuit comprising a current source transistor, a switching transistor and a current sink transistor coupled in series is provided. Control electrodes of the switching transistor and current sink transistor are directly connected and coupled to an input voltage. The buffer circuit has an accurate switchpoint voltage which is substantially process and temperature independent, and the circuit does not consume power for input voltages having low and high CMOS levels.

REFERENCES:
patent: 3651340 (1972-03-01), Cliff
patent: 3675144 (1972-07-01), Zuk
patent: 3980896 (1976-09-01), Kato
patent: 4274014 (1981-06-01), Schade, Jr.
patent: 4365316 (1982-12-01), Iwahashi et al.
patent: 4437024 (1984-03-01), Wacyk
patent: 4486671 (1984-12-01), Ong
patent: 4501978 (1985-02-01), Gentile et al.
Dingwall, "TTL-to-CMOS Buffer Circuit", RCA Technical Notes, TN No. 1114, Jun. 11, 1975 pp. 1-3.

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