TTL to CMOS input buffer circuit

Details TTL to CMOS input buffer circuit TTL to CMOS input buffer circuit

1979-03-19

1981-03-24

Dixon, Harold A.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307DIG1, H03K 1908

Patent

active

042582725

ABSTRACT:
A TTL to CMOS input buffer integrated circuit having an input terminal for connection to an output terminal of a TTL device is disclosed. The buffer circuit includes a first CMOS inverter connected to the input terminal, including a first p-channel FET connected to a supply terminal and a first n-channel FET connected to a ground terminal, wherein the drain of the first p-channel FET is connected to the drain of the first n-channel FET at a first node; a second n-channel FET having its gate connected to the input terminal and its source connected to the ground terminal; a third n-channel FET having its gate connected to the first node, its drain connected to the supply terminal, and its source connected to the drain of the second n-channel FET at a second node for forcing the potential at the second node to be less than the potential at the first node by the amount of the threshold voltage of the third n-channel FET; and a second p-channel FET having its gate connected to the second node, its source connected to the first node, its drain connected to the ground terminal, and its substrate connected to the supply terminal, for reducing the rate at which the third n-channel FET becomes conductive when gated on in a said integrated circuit in which the threshold of the n-channel FET's is greater than the threshold of the p-channel FET's.

REFERENCES:
patent: 3676700 (1972-07-01), Buchanan
patent: 4031409 (1977-06-01), Shimada et al.
"TTL-To-CMOS Buffer Circuit" by Andrew Dingwall, RCA Technical Notes, No. 1114, Jun. 11, 1975, 3 sheets.

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