TTL to CMOS input buffer

Details TTL to CMOS input buffer TTL to CMOS input buffer

1984-12-28

1986-06-03

Anagnos, Larry N.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307443, 307585, 307279, H03K 19017, H03K 3037, H03K 19094, H03K 19003

Patent

active

045932123

ABSTRACT:
A TTL to CMOS input buffer has a CMOS inverter for receiving the TTL signal on its input. The inverter has a P channel transistor coupled between VDD and the output of the inverter, which has relatively low gain so that there is very little current flow through the inverter when the TTL signal is at low voltage logic high. A switch is coupled between VDD and the output of the inverter. The switch couples VDD to the output of the inverter in response to the TTL signal switching from a logic high to a logic low.

REFERENCES:
patent: 4039862 (1977-08-01), Dingwall et al.
patent: 4295065 (1981-10-01), Hsieh et al.
patent: 4380710 (1983-04-01), Cohen et al.
patent: 4472647 (1984-09-01), Allgood et al.
patent: 4475050 (1984-10-01), Noufer
patent: 4490633 (1984-12-01), Noufer et al.
patent: 4501978 (1985-02-01), Gentile et al.
patent: 4504747 (1985-03-01), Smith et al.

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