TTL-to-CMOS buffer

Details TTL-to-CMOS buffer TTL-to-CMOS buffer

1987-01-05

1988-08-09

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307264, H03K 501, H03K 17687

Patent

active

047630221

ABSTRACT:
A TTL-to-CMOS converter consists of a plurality of N-channel and P-channel MOS transistors, each of which is fabricated so as to have a predetermined channel Width-to-Length ratio (W/L). The transistors are arranged to include an input complementary pair for accepting TTL-level signals and an output complementary pair for providing CMOS-level signals. An N-channel tracking transistor is coupled between the drain electrodes of the P-channel and N-channel transistors of the input complementary pair. The (W/L) of the tracking transistor is approximately 1/8 to to 1/7 times the (W/L) of the N-channel transistor of the input complementary pair. This arrangement establishes a converter switch point with a significantly greater degree of accuracy than otherwise attainable. A pull-up transistor has a gate electrode coupled to the input terminal of the input complementary pair and a drain electrode coupled to the input electrode of the output complementary pair. The pull-up transistor operates to pull the input terminal of the output complementary pair toward Vdd as the TTL logic level at the input of the Buffer goes low.

REFERENCES:
patent: 4000411 (1976-12-01), Sano et al.
patent: 4080539 (1978-03-01), Stewart
patent: 4424456 (1984-01-01), Shiraki et al.
patent: 4486670 (1984-12-01), Chan et al.

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