TTL technology digital timing unit

Details TTL technology digital timing unit TTL technology digital timing unit

1987-06-01

1990-08-21

Heyman, John S.

Electrical pulse counters, pulse dividers, or shift registers: c

Systems

Using shift register

377 43, 328 63, 328155, H03K 2354, H03K 5153, H03K 513

Patent

active

049513010

ABSTRACT:
Timing unit for generating a timing signal for synchronous microprocessors in which an oscillator generates a base frequency equal to four times the timing frequency for the microprocessor. A frequency divider divides the base frequency by four, and a shift register clocked by the base frequency and receiving a timing signal from the frequency divider, generates a mask signal. The mask signal is selectively applied to a control input of the frequency divider in response to one or more control signals, to inhibit the switching of the frequency divider. This thereby introduces in the phases of the timing frequency, wait states equal to 1/4 (or multiple thereof) of the timing frequency, thereby matching the microprocessor speed to the memory read/write cycle time.

REFERENCES:
patent: 4105979 (1978-08-01), Kage
patent: 4390960 (1983-06-01), Yamashita et al.
patent: 4504960 (1985-03-01), Yamada
patent: 4564953 (1986-01-01), Werking
patent: 4641044 (1987-02-01), Shiraishi
patent: 4656649 (1987-04-01), Takahashi
Sundararajan et al., "Multiple-Wait-State Generator Handles Slow Peripherals", Electronic Design, Aug. 18, 1983, pp. 228-229.
Verkutzer Wait-Zyklus Beschleunigt 68000-Systeme, Pal Poth, Elektronik, No. 3, Oct. 2, 1984, pp. 59-60.

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