TTL flip-flop with clamping diode for eliminating race condition

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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307264, 307291, 307443, 307551, 307559, 307247R, G11C 1140, H03K 3289, H03K 508

Patent

active

044917457

ABSTRACT:
A master slave flip-flop includes a data gate for receiving the input data and generating therefrom first and second internal data signals, and a master section for latching the internal data signals and for transmitting such signals to a slave section during predetermined portions of a clock signal. In order to render the internal data signals symmetrical with respect to each other and therefore substantially reduce the possibility of transmitting incorrect data to the slave as a result of a race condition in the master section, a Schottky diode is coupled within the data gate to complete a discharge path for one of the internal data lines and thus prevent it from exceeding a predetermined voltage.

REFERENCES:
patent: 3751683 (1973-08-01), Drost
patent: 3828206 (1974-08-01), Zuk
patent: 3993918 (1976-11-01), Sinclair
patent: 3996478 (1976-12-01), Kasperkovitz
patent: 4027176 (1977-05-01), Heuber et al.
Wu, "Master-Slave Flip-Flop",IBM Tech. Disc. Bull., vol 16, No. 7, Dec. 1973, pp. 2131-2132.

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