TTL compatible CMOS logic circuit for driving heavy capacitive l

Details TTL compatible CMOS logic circuit for driving heavy capacitive l TTL compatible CMOS logic circuit for driving heavy capacitive l

1987-12-09

1989-09-19

Hudspeth, David

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307362, 307443, 307475, H03K 19003

Patent

active

048684228

ABSTRACT:
CMOS logic circuit with one or more inputs has at least a complementary pair of transistors, the N-channel driver transistor having a gate directly connected to an input while the P-channel load transistor having a gate connected to the output of the second one of two inverters connected in cascade, the input of the first inverter being connected to the input of the circuit. Using two signal inverting stages or inverters for mirroring the input signal on the gate of the load P-channel transistor of the circuit pair permits the defining of the triggering threshold of the circuit with great freedom, the obtaining of a greater switching speed and the reduction of power dissipation under stand-by conditions. The invention is particularly suited for HCT circuits.

REFERENCES:
patent: 4486670 (1984-12-01), Chan et al.
patent: 4645952 (1987-02-01), van Tran
patent: 4698526 (1987-10-01), Allan
patent: 4703199 (1987-10-01), Ely
patent: 4728827 (1988-03-01), Woo
Hoffman, "Positive Voltage Translation Circuit", IBM T.D.B., vol. 17, No. 8, Jan. 1975, pp. 2392-2393.
Banker et al., "Receiver for Off-Module Mixed Technology Nets", IBM T.D.B., vol. 23, No. 6, Nov. 1980, pp. 2301-2302.

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