TTL Compatible CMOS input buffer

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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307443, 307451, H03K 19003, H03K 19092, H03K 19094, H03K 502

Patent

active

044383525

ABSTRACT:
A circuit for converting a digital signal from TTL to CMOS levels. The circuit delay is reduced by providing a transmission gate between the P and N type transistors in the first stage. This transmission gate has a high impedance during transistions and a low impedance during steady state conditions. In operation, for a rising input signal, the first stage transistors are isolated, allowing the first stage N type transistor to pull down the first stage output line without delay.

REFERENCES:
patent: 3675144 (1972-07-01), Zuk
patent: 4295065 (1981-10-01), Hsieh et al.
patent: 4321491 (1982-03-01), Atherton et al.
Dingwall, "TTL-to-CMOS Buffer Circuit"; RCA Technical Notes; TN No.: 1114, 3 pp., 6/1975.

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