TTL-compatible cell for CMOS integrated circuits

Details TTL-compatible cell for CMOS integrated circuits TTL-compatible cell for CMOS integrated circuits

1988-03-23

1989-12-19

Heyman, John S.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

3072963, 307451, H03K 19092, H03K 301, H03K 19094

Patent

active

048885002

ABSTRACT:
The TTL-compatible cell comprising two cascade coupled CMOS inverters is associated with an input pin of the integrated circuit to make it suitable to receive signals in TTL logic, as well as with a power-down pin, and is characterized in that said input (10) of the CMOS integrated circuit is connected to the input of the first of said two inverters (12, 14) through a first and a second respectively P-channel and N-channel MOS transistor in parallel (28, 30), the first controlled by the power-down pin (31), the second by an inverter (32) driven by said power-down pin, so as to be both off when the power-down signal is at logical 1 and active when the power-down signal is at logical 0. Between the input of the first inverter and the ground a further MOS transistor (34) is connected the gate whereof is controlled so that said further MOS transistor is active when the power-down signal is at logical 1 and is off when the power-down signal is at logical 0.

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