TTL-Compatible address latch with field effect transistors

Details TTL-Compatible address latch with field effect transistors TTL-Compatible address latch with field effect transistors

1979-08-14

1981-11-17

Zazworsky, John

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307264, 307279, H03K 500, H03K 3356

Patent

active

043013813

ABSTRACT:
Disclosed is a field effect transistor (FET) circuit for accepting a bipolar transistor logic level input signal and providing FET logic level output signals (both in-phase and out-of-phase components). The FET circuit includes a gated latch with means for pre-charging first and second nodes to an FET logic up level. One of the two nodes is brought to a slightly higher or lower level (depending on the binary value of the input), thereby producing a latent imbalance in the latch. A gating signal causes the latch to switch into the state pre-set by the latent imbalance.

REFERENCES:
patent: 3969706 (1976-07-01), Proebsting et al.
patent: 4000413 (1976-12-01), Wong et al.
patent: 4038567 (1977-07-01), Lewis et al.
patent: 4104733 (1978-08-01), Satoh
patent: 4149099 (1979-04-01), Nagami
IBM-TDB "Address Buffer True/Complement Generator", A. Furman, vol. 18, No. 11, Apr. 1976, pp. 3597-3598.
IBM-TDB, "Bipolar Logic Level to FET Logic Level Buffer Circuit", S. Lewis et al., vol. 19, No. 8, Jan. 1977, pp. 2953-2954.
IBM-TDB "True and Complement High Level Signal Circuit", Parikh, vol. 20, No. 3, Aug. 1977, pp. 954-955.

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