TTL/CMOS level translator

Details TTL/CMOS level translator TTL/CMOS level translator

1989-09-12

1990-10-16

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307451, 307542, 307572, H03K 1716, H03K 190175

Patent

active

049637711

ABSTRACT:
The present invention implements a static inverter-type TTL/CMOS level translator. The present invention utilizes a pair of transistors to suppress hot electron effects. The transistor pair limits maximum VDS to VCC-VTN at the first and second gain stages. A pair of resistors serve as a virtual VCC modulator to minimize voltage variations, stabilizing the VIL/VIH trip point. The resistors also minimize standby current so that the translator of the present invention can be used in a low standby current environment. The translator of the present invention provides faster speed, wider process margins, better reliability and lower standby current than prior art translators.

REFERENCES:
patent: 4209713 (1980-06-01), Satou et al.
patent: 4806801 (1989-02-01), Argade et al.

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