TTL buffer circuit incorporating active pull-down transistor

Details TTL buffer circuit incorporating active pull-down transistor TTL buffer circuit incorporating active pull-down transistor

1983-11-22

1987-01-06

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307443, 307270, H03K 19013, H03K 19088, H03K 1704, H03K 1760

Patent

active

046348980

ABSTRACT:
A unique double inversion buffer has a first means to invert and isolate the digital input signal, a second means to reinvert and further isolate the input signal, and an output means including an output transistor 94. The double inversion buffer is configured with active pull-down means on the output transistor 92. The high-to-low propagation delay time and the low-to-high propagation delay times through the double inversion buffer and reduced by use of the active pull-down means. Rapid turnoff of the output transistor is accomplished by coupling a transistor to its base to instantaneously turn it off. In a preferred embodiment, a clamping circuit 201 is used to hold the output voltage at a maximum predetermined level to further reduce the time it takes to reduce the output voltage to the logical "0" state.

REFERENCES:
patent: 3602735 (1971-08-01), Lodi
patent: 4330723 (1982-05-01), Griffith
patent: 4339675 (1982-07-01), Ramsey
patent: 4347446 (1982-08-01), Price
patent: 4349751 (1982-09-01), Hartman et al.
patent: 4449063 (1984-05-01), Ohmichi et al.
patent: 4458162 (1984-07-01), Solomon et al.
A. W. Chang, IBM Technical Disclosure Bulletin, vol. 20, No. 2, Jul., 1977, pp. 601-603.

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