Electricity: electrical systems and devices – Housing or mounting assemblies with diverse electrical... – For electronic systems and devices
Reexamination Certificate
2002-01-15
2003-03-25
Cuneo, Kamand (Department: 2827)
Electricity: electrical systems and devices
Housing or mounting assemblies with diverse electrical...
For electronic systems and devices
C257S686000, C257S692000
Reexamination Certificate
active
06538895
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to a configuration of at least two TSOP memory chip housings stacked one on another and a rewiring configuration formed as a leadframe having connecting lines with free ends. The TSOP memory chip housings have contours of identical cross section, including a first TSOP memory chip housing and a second TSOP memory chip housing, stacked one on another. Each of the two TSOP memory chip housings have an interior and at least one memory chip with a number of pins disposed in the interior of each of the two TSOP memory chip housings. The leadframe is disposed between the two TSOP memory chip housings or at a side between the two TSOP memory chip housings. The pins leading out of the first TSOP memory chip housing are connected through the leadframe to the pins leading out of the second TSOP memory chip housing. The pins have ends leading out of the two TSOP memory chip housings and the ends are formed in a shape of s-shaped ends in cross-section, step-shaped ends in cross section, kinked over downward ends or kinked over upward ends. The pins of different ones of the TSOP memory chip housings are disposed one over another and aligned in parallel with one another in space.
The thin small online package (TSOP) memory chip housings contain in their interior at least one memory chip, which has a number of pins which are led out of the respective TSOP memory chip housing. The storage capacity of such TSOP memory chip housings can be multiplied by stacking individual housings one on another. At the same time, however, care must be taken that identically wired memory chips are driven by different pins. It is therefore necessary, and has already been proposed, to provide a rewiring plane which, at the same time, connects the respective pins of the housings stacked one on another to one another.
It has already been proposed to implement such TSOP memory chip housings stacked one on another with the aid of small integrated circuits (printed circuit boards), or with the aid of connecting leadframes (“leadframes”) on the outside of the housing and with flexible materials (with bent-over legs) between the individual housings.
The proposed solutions are relatively complicated and can be used only conditionally for cost-effective automation of the manufacture of such housing stacks.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a TSOP memory chip housing configuration which overcomes the above-mentioned disadvantages of the prior art devices of this general type, which is cost-effective in terms of its manufacture and in addition is suitable for automated manufacture.
With the foregoing and other objects in view there is provided, in accordance with the invention, a configuration containing a rewiring configuration formed as a leadframe having connecting lines with free ends. The free ends have a cross-sectional shape being groove-shaped free ends, trough-shaped free ends, u-shaped free ends or v-shaped free ends. At least two thin small online package (TSOP) memory chip housings are provided and have contours of identical cross section, including a first TSOP memory chip housing and a second TSOP memory chip housing, stacked one on another. Each of the two TSOP memory chip housings have an interior and at least one memory chip with a number of pins disposed in the interior of each of the two TSOP memory chip housings. The leadframe is disposed between the two TSOP memory chip housings or at a side between the two TSOP memory chip housings. The pins leading out of the first TSOP memory chip housing are connected through the leadframe to the pins leading out of the second TSOP memory chip housing. The pins have ends leading out of the two TSOP memory chip housings and the ends are formed as s-shaped ends in cross-section, step-shaped ends in cross section, kinked over downward ends or kinked over upward ends. The pins of different ones of the two TSOP memory chip housings are disposed one over another and aligned in parallel with one another in space.
The pins leading out of the respective TSOP memory chip housing and are connected to the respectively directly adjacent TSOP memory chip housing of the same TSOP memory chip housing stack via a rewiring configuration. The invention provides for the rewiring configuration to be implemented in the form of leadframes in each case disposed between or at the side between the individual TSOP memory chip housings.
The result of introducing the rewiring or connecting plane by leadframes between the individual housings or at the side between the housings is a series of advantages as compared with the other solutions already proposed and outlined further above. First, significant cost savings are achieved as a result of using the leadframe technique, known per se. Second, the introduction of rewiring planes between the housings is straightforwardly possible. Third, well-defined soldering areas can be defined in a straightforward way; the application of a solder deposit is possible. Fourth, lateral-soldering methods, such as a mini solder wave can be implemented.
In accordance with an added feature of the invention, the connecting lines of the leadframe are shaped at the free ends such that the free ends connect the pins in each case located directly one next another of the two TSOP memory chip housings.
In accordance with additional feature of the invention, at least one of the two TSOP memory chip housings is connected mechanically to the leadframe, preferably by an adhesive bond.
In accordance with a further feature of the invention, the pins are soldered or welded to the free ends of the connecting lines of the leadframe.
With the foregoing and other objects in view there is provided, in accordance with the invention, a configuration containing thin small online package (TSOP) memory chip housings having contours of identical cross section. Each of the TSOP memory chip housings have an interior and at least one memory chip with a number of pins disposed in the interior of each of the TSOP memory chip housings and the pins lead out of the TSOP memory chip housings. A plurality of leadframes are provided and each have connecting lines with free ends. The free ends have a cross-sectional shape being groove-shaped free ends, trough-shaped free ends, u-shaped free ends or v-shaped free ends. Each of the leadframes is disposed between two of the TSOP memory chip housings or at a side between two of the TSOP memory chip housings. A respective one of the leadframes and a respective two of the TSOP memory chip housings including a first TSOP memory chip housing and a second TSOP memory chip housing, stacked one on another with the respective leadframe disposed inbetween forms one of a plurality of stacks. The pins leading out of the first TSOP memory chip housing are connected through the respective leadframe to the pins leading out of the second TSOP memory chip housing. The pins have ends leading out of the two TSOP memory chip housings and the ends are formed as s-shaped ends in cross-section, step-shaped ends in cross section, kinked over downward ends or kinked over upward ends. The pins of different ones of the two TSOP memory chip housings are disposed one over another and aligned in parallel with one another in space.
In accordance with a concomitant feature of the invention, a common carrier is provided, and at least two of the stacks are disposed beside one another, and in that the leadframes of the at least two stacks are disposed on the common carrier.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a TSOP memory chip housing configuration, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
REFERENCES:
patent: 514781
Gottlieb Alfred
Römer Bernd
Wörz Andreas
Cruz L.
Cuneo Kamand
Greenberg Laurence A.
Infineon - Technologies AG
Locher Ralph E.
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