True/complement generator employing feedback circuit means for c

Details True/complement generator employing feedback circuit means for c True/complement generator employing feedback circuit means for c

1982-12-09

1985-07-16

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307443, 307456, 307269, 307601, 328 55, 328 57, 328155, H03K 515, H03K 19088, H03K 1920

Patent

active

045298963

ABSTRACT:
A true/complement generator for generating the complement and true value of weighted address bits, preventing an address decoder from selecting several lines at the same time. It comprises two circuits (1) and (2), the first one providing the true value (.phi.), the second one providing the complement (.phi.) thereof. The means provided for preventing multiple selections from occurring, comprise in the first circuit, a transistor (T11-1) for delaying the rising edge of (.phi.) as long as it is maintained on by the level provided by resistors R11-1 and R10-2 from output .phi.. Transistor T11-2 in the second circuit prevents .phi. from going high as long as it is maintained on by the level provided by R10-1, R11-2 from .phi..

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"Dynamic Mosfet Logic Clock Driver", B. Cassidy et al., vol. 22, No. 3, Aug. 1979, IBM Technical Disclosure Bulletin.
"True-Complement Generator" by S. D. Koutos et al., IBM Technical Disclosure Bulletin, vol. 14, No. 11, Apr. 1972, p. 3244.
"In-Line Word Address True/Complement Generator" by A. Denis et al., IBM Technical Disclosure Bulletin, vol. 24, No. 4, Sep. 1981, p. 2209.
Publication No. 0024496 of the European Patent Application filed on Jun. 24, 1980 (Publication No. 0024496 Corresponds to U.S. patent application Ser. No. 179,210 entitled "Generator Circuit for Generating True/Complement Signals", filed 8/18/80 by Grandguillot et al., of common assignee and now abandoned.

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