Tristate output gate structure particularly for CMOS integrated

Details Tristate output gate structure particularly for CMOS integrated Tristate output gate structure particularly for CMOS integrated

1991-06-21

1993-04-06

Westin, Edward P.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307475, 307451, 307443, H03K 19017, H03K 19094

Patent

active

052006530

ABSTRACT:
The tristate output gate structure particularly for CMOS integrated circuits, comprises an enable terminal receiving an enable signal and an input terminal receiving an input signal, which connects, through signal switching means, an output terminal to a positive power supply terminal or to a negative power supply terminal. The enable terminal can be electrically connected to the gate terminal of a first P-channel transistor through signal inverting means and to the gate terminal of a second N-channel transistor. The output terminal is electrically connected to the drain terminals of the first and second transistors. The first and second transistors electrically insulate the output terminal from the input terminal.

REFERENCES:
patent: 4345172 (1982-08-01), Kobayashi et al.
patent: 4465945 (1984-08-01), Yin
patent: 4717846 (1988-01-01), Ando
patent: 5027012 (1991-06-01), Saeki et al.
patent: 5034637 (1991-07-01), Jungert

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