Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons
Patent
1990-07-19
1992-06-02
Westin, Edward P.
Electrical transmission or interconnection systems
Nonlinear reactor systems
Parametrons
307475, 307456, 307300, H03K 19092, H03K 1900
Patent
active
051189747
ABSTRACT:
A FAST OE signal circuit generates FAST OE signals of high and low potential levels. A SLOW OE signal circuit generates SLOW OE signals corresponding to FAST OE signals. The SLOW OE signals have the same high or low potential level as the corresponding FAST OE signals and occur a specified time delay after the corresponding FAST OE signals. A tristate output buffer circuit operates in the bistate mode when enabled by high potential level OE signals for transmitting binary data signals, and operates in a high Z tristate mode when disabled by low potential level OE signals. The FAST OE signal circuit and SLOW OE signal circuit ae coupled in parallel to the tristate output buffer circuit for enabling and disabling the tristate output buffer circuit. The FAST and SLOW OE signals in combination skew the enable time relative to the disable time. The enable times tpZH and tpZL are substantailly longer than the disable times tpHZ and tpLZ, introducing "temporal" separation between active tristate output devices on a common bus to reduce bus contention. A DC Miller killer circuit is coupled to the pulldown transistor element of the tristate output buffer circuit for turning off and holding off the pulldown transistor element in response to high potential level DCMK signals. A DCMK signal circuit generates DCMK signals corresponding to inverted FAST OE signals. A DCMK signal enhancer circuit provides transient enhancement of high potential level DCMK signals in response to corresponding low potential level FAST and SLOW OE signals.
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Quiet Duane G.
Yarbrough Roy L.
Kane Daniel H.
National Semiconductor Corporation
Rose James W.
Roseen Richard
Westin Edward P.
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