Triple self-aligned metallurgy for semiconductor devices

Details Triple self-aligned metallurgy for semiconductor devices Triple self-aligned metallurgy for semiconductor devices

1992-06-03

1993-02-23

Wojciechowicz, Edward J.

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

257758, 257774, H01L 2348

Patent

active

051895064

ABSTRACT:
A process is described which eliminates the need to account for mask alignment tolerances in forming vias for metallurgy by the use of a common vertical edge or common plane defined by a first mask representing a first level of interconnect. Subsequent masks for defining interconnecting vias and a second level of interconnect utilize at least one edge of the first mask pattern as a common element to define subsequent metal levels. The combination of an etch stop layer and an oversized second level mask enable the mask overlay to be eliminated.

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patent: 4789648 (1988-12-01), Chow et al.
patent: 4892843 (1990-01-01), Schmitz
IBM TDB-Cronin et al.-vol. 31, No. 4, Sep. 1988 pp. 400-401.
IBM TDB, vol. 30, #7, Dec. 1987, pp. 195-196, "Single Mask and Imaging For A Dual Level Self Aligned Definition", J. E. Cronin.
Patent Application 516,394 (BU-9-89-025), J. E. Cronin et al., "Process for Forming Multi-Level Coplanar Conductor/Insulator Films Employing Photosensitive Polyimide Polymer Compositions".
"Polyimide Film Properties and Selective LPCVD of tungsten on Polyimide" R. W. Patee et al., J. Electrochemical Society, Jun. 1988, pp. 1477-1483.
1988 Symposium on VLSI Technology Digest of Technical Papers, pp. 71-72, May 10-13, K. Mitsuhashi et al., "Thermally Stable . . . ".
Patent Application 337,807 (BU-9-86-005A), J. E. Cronin et al., "A Multi-Level Integrated Circuit Wiring Structure from a Single Metal Deposit".

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