Triple register RISC digital signal processor

Details Triple register RISC digital signal processor Triple register RISC digital signal processor

1995-10-23

1996-12-17

Lane, Jack A.

395401, G06F 1200

Patent

active

055862845

ABSTRACT:
The STREAMER FOR RISC DIGITAL SIGNAL PROCESSOR shown herein allows a CPU 46 to interface with a memory 60 via data registers 50. Pre-fetch and post-store of the correct address is determined by an address generator 58 according to a rule determined by a context register 52. An index indicative of this address is stored in an index register 54. The data, context, and index registers together form a streamer 56, streaming data between the CPU 46 and data memory 60. The rule of the context register 52 also drives a converter 62 for converting data between memory format and register format. The speed and flexibility of a RISC device is combined with the intensive memory access of a digital signal processor.

REFERENCES:
patent: 3454932 (1969-07-01), Bahrs et al.
patent: 4131940 (1978-12-01), Moyer
patent: 4550368 (1985-10-01), Bechtolsheim
patent: 5218674 (1993-06-01), Peaslee et al.
patent: 5222222 (1993-06-01), Mehring et al.
patent: 5309156 (1994-05-01), Fujiyama

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