Triple redundant latch design with storage node recovery

Details Triple redundant latch design with storage node recovery Triple redundant latch design with storage node recovery

2005-08-16

2005-08-16

Lam, Tuan T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

C327S208000, C327S218000

Reexamination Certificate

active

06930527

ABSTRACT:
In a preferred embodiment, the invention provides a circuit and method for a smaller and faster triple redundant latch with storage node recovery. An input driver is connected to the input of three transfer gates. The output of each transfer gate is connected to a separate output of one of three feedback inverters. The transfer gates are controlled by two control inputs. The inputs of the three feedback inverters are connected the output of the forward inverter/majority voter. The output from each of the three feedback inverters are inputs to the forward inverter/majority voter. The output of the forward inverter/majority voter is connected to the input of the output driver. The output of the output driver is the output of the triple redundant latch.

REFERENCES:
patent: 6127864 (2000-10-01), Mavis et al.
patent: 6504411 (2003-01-01), Cartagena
patent: 6667520 (2003-12-01), Fulkerson
patent: 6825691 (2004-11-01), Chu et al.
patent: 2004/0246782 (2004-12-01), Chu et al.

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