Triple redundant latch design using a fail-over mechanism...

Details Triple redundant latch design using a fail-over mechanism... Triple redundant latch design using a fail-over mechanism...

2005-04-19

2005-04-19

Lam, Tuan T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

C327S208000, C327S218000

Reexamination Certificate

active

06882201

ABSTRACT:
In a preferred embodiment, the invention provides a circuit and method for a smaller and faster triple redundant latch. An input driver is connected to the input of two transfer gates. The output of one transfer gate is connected to an I/O of a first latch and the output of the second transfer gate is connected to the I/O of a second latch. The I/O of the first latch is connected to a first input of a tristatable input inverter. The I/O of the second latch is connected to a second input of the tristatable input inverter. The output of the tristatable input inverter is connected to the I/O of a third latch and the input of an output driver.

REFERENCES:
patent: 5111429 (1992-05-01), Whitaker
patent: 5311070 (1994-05-01), Dooley
patent: 5870332 (1999-02-01), Lahey et al.
patent: 6127864 (2000-10-01), Mavis et al.
patent: 6504411 (2003-01-01), Cartagena

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