Triple-poly 4T static ram cell with two independent transistor g

Details Triple-poly 4T static ram cell with two independent transistor g Triple-poly 4T static ram cell with two independent transistor g

1988-12-07

1990-08-21

Larkins, William D.

Static information storage and retrieval

Magnetic bubbles

Guide structure

357 239, 357 59, 365154, H01L 2711, G11C 11412

Patent

active

049511122

ABSTRACT:
A 4T static RAM cell (10) comprising a flip-flop with two pull-down transistors (18, 20) and two pass-gate transistors (12, 14) is fabaricated employing two separate gate oxide formations (74, 76) and associated separate polysilicon depositions (52a -b, 56). Two reduced area contacts (58, 60) connect to the nodes (26, 30) of the circuit (10). The reduced area butting contacts comprise vertically-disposed, doped polysilicon plugs (94), which intersect and electrically interconnect buried polysilicon layers (load poly 88, gate poly 52a) with doped silicon regions (80) in a bottom layer. Adding the processing steps of forming separate gate oxides for the pull-down and pass-gate transistors results in a smaller cell area and reduces the requirements of the contacts from three to two. Further, the separate gate oxidations permit independent optimization of the pull-down and pass-gate transistors.

REFERENCES:
patent: 3949383 (1976-04-01), Askin et al.
patent: 4023149 (1977-05-01), Bormann et al.
patent: 4240097 (1980-12-01), Raymond, Jr.
patent: 4525811 (1985-06-01), Masuoka
patent: 4679171 (1987-07-01), Logwood et al.
Geipel, Jr. et al., IEEE Trans. on Electron Devices, vol. ED27, No. 8, Aug. 1980, p. 1417.

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