Patent
1996-05-21
1999-02-02
Lall, Parshotam S.
395309, 395872, G06F 1338
Patent
active
058676724
ABSTRACT:
A buffer IC includes two FIFO buffers accessible in a triple-bus configuration including a bi-directional port, an input port, and an output port. Each of the ports uses a fall-through timing which facilitates interconnection of similar buffer ICs into a chain to expand the depth of a FIFO buffer. Typically, the input and output ports have a data width that differs from the data width of the bi-directional bus the FIFO buffers perform bus matching. One type of bus matching collects data values from the smaller width port to form larger width values for output from the larger port. Another type of bus matching splits data values from the larger width port to form data values for output from the smaller port.
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Integrated Device Technology Data Book, Sec. 5.16, "CMOS SyncBiFIFO 256.times.36.times.2, 512.times.36.times.2, 1024.times.36.times.2", Integrated Device Technology, Jan. 1995, pp. 1-26.
Au Mario F.
Wang Eugene D.
Integrated Device Technology Inc.
Lall Parshotam S.
Vu Viet
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