Triple buffered amplifier output stage

Amplifiers – With semiconductor amplifying device – Including push-pull amplifier

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Details

330267, H03F 326

Patent

active

055150071

ABSTRACT:
In a triple buffer stage output stage applicable to an operational amplifier, the two transistors in the first buffer stage are bootstrapped to the second buffer stage. The collector voltage of each transistor in the first buffer stage thereby follows the input signal at the high impedance node and therefore their parasitic capacitance to the substrate does not have a significant effect. This bootstrapping the collectors of the transistors of the first buffer stage minimizes parasitic capacitance effects and improves phase delay of the output stage. Additionally, the PNP transistors in the signal path of the output stage are fabricated in isolated N-wells to minimize the effect of the N-well to collector capacitance, the N-wells of the signal path PNP transistors which are reverse biased also being bootstrapped. Also provided in the output stage are an RC network connected between the input node of the output stage and its output terminal, and damping resistors to dampen peaking at higher frequencies and minimize temperature effects on amplifier performance. In a second embodiment, the two transistors in the first buffer stage each has multiple additional emitters, each connected to the output terminal. This bootstraps the output stage at lower frequencies, improving performance.

REFERENCES:
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patent: 4827223 (1989-05-01), Gross
patent: 4833424 (1989-05-01), Wright
patent: 4894622 (1990-01-01), Buitendijk
patent: 4970470 (1990-11-01), Gosser
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patent: 5218321 (1993-06-01), Jost
patent: 5323122 (1994-06-01), Bowers
patent: 5339042 (1994-08-01), Kaire et al.

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