Trinary check trit generator, latch, comparator and multiplexer

Details Trinary check trit generator, latch, comparator and multiplexer Trinary check trit generator, latch, comparator and multiplexer

1990-05-03

1992-06-16

Hudspeth, David

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307243, 307360, 307443, 365168, 371 56, H03K 1920

Patent

active

051226880

ABSTRACT:
A method and apparatus for performing data error detection and correction is disclosed for multi-level logic and in particular, three-level trinary logic of levels 0, 1, 2. A source of trinary data supplies individual pieces of data (trits of 0, or 1, or 2) in multiple trit groups (trytes) to two separate check trit generators which generate unique check trits for each tryte input. The check trits from the two check trit generators are compared to form syndrome trits which are used to control an error detection function. For single errors per tryte a data correction function is activated to increment or decrement the incorrect data through a multiplexer. Multiple errors or no error conditions are indicated, but do not gate the data correction function.

REFERENCES:
patent: 3866147 (1975-02-01), DeCouvreur et al.
patent: 4244052 (1981-01-01), Hemsworth
patent: 4518875 (1985-05-01), Aytac
patent: 4631428 (1986-12-01), Grimes
patent: 4661801 (1987-04-01), Chen et al.
patent: 4808854 (1989-02-01), Reinagel
patent: 4910750 (1990-03-01), Fisher
patent: 4961192 (1990-10-01), Grimes
Grimes, "Ternary CMOL Logic Device", IBM T. D. B., vol. 17, No. 4, Sep. 1974, pp. 1145-1146.
"Trinary Logic Circuits", IBM T. D. B., vol. 31, No. 3, Aug. 1988, pp. 48-56.
Moley et al., "Auto-Reset Ternary Latch", IBM T. D. B., vol. 14, No. 2, Jul. 1971, pp. 630-631.

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