Static information storage and retrieval – Powering
Reexamination Certificate
1999-11-19
2001-10-23
Nelms, David (Department: 2818)
Static information storage and retrieval
Powering
C365S233500
Reexamination Certificate
active
06307801
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to semiconductor integrated circuits, and more particularly, to a system circuit incorporating memories and logic circuits.
The demand for combined memory/logic type system LSIs has increased in recent years. In such a system LSI, a plurality of memories are incorporated in a single device to meet the demands for decreasing power consumption and providing more functions. There is also a demand for decreasing the time required for testing the system LSI.
FIG. 1
shows an example of a prior art system LSI. The system LSI
1
includes two memory macros
2
,
3
, each having a memory capacity of 2MB, a memory macro
4
having a memory capacity of 8MB, and two logic circuits
5
,
6
. All of the circuits
2
-
6
are arranged at predetermined positions on a chip. Referring to
FIG. 2
, as known in the prior art, each of the memory macros
2
-
4
includes a memory cell array
10
, a row decoder
11
, a column decoder
12
, an input/output circuit
13
, an input buffer circuit
14
, a mixer
15
, and a power supply circuit
16
. The memory macros
2
,
3
differ from the memory macro
4
only in memory capacity and circuit scale, which is related to the memory capacity.
The power supply circuit
16
includes a pull-down circuit
20
, which is shown in FIG.
3
. The pull-down circuit
20
is provided with a trimming circuit
21
, a reference voltage generating circuit
22
, a control circuit
23
, and a power supply driver circuit
24
. The control circuit
23
receives an enable signal EN. The control circuit
23
shifts the power supply driver circuit
24
between an activated state and a deactivated state in accordance with the enable signal EN. The reference voltage generating circuit
22
sends a reference voltage V
r
to the power supply driver circuit
24
. The power supply driver circuit
24
decreases the voltage of an external power supply based on the reference voltage V
r
and generates an internal power supply V
in
. The internal power supply V
in
is sent to, for example, the memory cell array
10
as an operational power supply.
As shown in
FIG. 4
, the trimming circuit
21
includes two fuse circuits
31
,
32
and four AND circuits
33
-
36
. The fuse circuit
31
has a first NMOS transistor T
r1
, a fuse f
01
, and two inverters
31
a
,
31
b
. The source of the first NMOS transistor T
r1
is connected to a low potential power supply V
SS
. The drain of the first NMOS transistor T
r1
is connected to the high potential power supply V
CC
via the fuse f
01
and to its gate via the inverter
31
a
. The drain of the first NMOS transistor T
r1
outputs a detection signal n
01
z. The detection signal n
01
z is inverted by the inverter
31
b
and output as a detection signal n
01
x.
The fuse circuit
32
has a second NMOS transistor T
r2
, a fuse f
02
, and two inverters
32
a
,
32
b
. The structure of the fuse circuit
32
is identical to that of the fuse circuit
31
. The drain of the second NMOS transistor T
r2
outputs a detection signal n
02
z. The detection signal n
02
x is also output from the drain of the second NMOS transistor Tr
2
via the inverter
32
b
.
The detection signals n
01
x, n
02
z are received by the first AND circuit
33
. An output voltage V
1
is output from the output terminal of the first AND circuit
33
in accordance with the signals n
01
x, n
02
z. The detection signals n
01
z, n
02
z are received by the second AND circuit
34
. An output voltage V
2
is output from the output terminal of the second AND circuit
34
in accordance with the signals n
01
z, n
02
z. The detection signals n
01
z, n
02
x are received by the third AND circuit
35
. An output voltage V
3
is output from the output terminal of the third AND circuit
35
in accordance with the signals n
01
z, n
02
x. The detection signals n
01
x, n
02
x are received by the fourth AND circuit
36
. An output voltage V
4
is output from the output terminal of the fourth AND circuit
36
in accordance with the signals n
01
x, n
02
x. The first to third AND circuits
33
-
35
are each connected to the reference voltage generating circuit
22
.
As shown in
FIG. 4
, the reference voltage generating circuit
22
includes a resistor R and seven NMOS transistors T
r3
-T
r9
. The resistor R and the four NMOS transistors T
r3
-T
r6
are connected in series between the high potential power supply V
CC
and the low potential power supply V
SS
. The gate and drain of each NMOS transistor T
r3
-T
r6
are connected to each other. That is, each of the NMOS transistors T
r3
-T
r6
acts as a diode.
The source of the third NMOS transistor T
r3
is connected to the low potential power supply V
SS
via the seventh NMOS transistor T
r7
. The drain of the third NMOS transistor T
r3
is an output node. The reference voltage V
r
is sent from the output node to a measuring pad P, which is arranged on the power supply driver circuit
24
. The gate of the seventh NMOS transistor T
r7
receives the output voltage V
1
. The source of the fourth NMOS transistor T
r4
is connected to the low potential power supply V
SS
via the eighth NMOS transistor T
r8
. The gate of the eighth NMOS transistor T
r8
receives the output voltage V
2
. The source of the fifth NMOS transistor T
r5
is connected to the low potential power supply V
SS
via the ninth NMOS transistor T
r9
. The gate of the ninth NMOS transistor T
r9
receives the output voltage V
3
.
As shown in
FIG. 5
, in the trimming circuit
21
and the reference voltage generating circuit
22
, only the output voltage V
2
goes high when both fuses f
01
, f
02
do not undergo trimming (as indicated by the circles). In this case, the eighth NMOS transistor T
r8
is activated. Accordingly, the reference voltage V
r
has a level obtained by distributing the potential difference between the high potential power supply V
CC
and the low potential power supply V
SS
to the resistor R and the ON resistance of the two NMOS transistors T
r3
, T
r4
.
If trimming is performed on only the fuse f
01
(as marked by the “X”), only the output voltage V
1
goes high. In this case, the seventh NMOS transistor T
r7
is activated. Accordingly, the reference voltage V
r
has a level obtained by distributing the potential difference between the high potential power supply V
CC
and the low potential power supply V
SS
to the resistor R and the ON resistance of the third NMOS transistor T
r3
.
If trimming is performed on only the fuse f
02
, only the output voltage V
3
goes high. In this case, the ninth NMOS transistor T
r9
is activated. Accordingly, the reference voltage V
r
has a level obtained by distributing the potential difference between the high potential power supply V
CC
and the low potential power supply V
SS
to the resistor R and the ON resistance of the three NMOS transistors T
r3
-T
r5
.
If trimming is performed on both of the fuses f
01
, f
02
, only the output voltage V
4
goes high, while output voltages V
1
-V
3
all go low. Accordingly, the NMOS transistors T
r7
-T
r9
remain deactivated. As a result, the reference voltage V
r
has a level obtained by distributing the potential difference between the high potential power supply V
CC
and the low potential power supply V
SS
to the resistor R and the ON resistance of the four NMOS transistors T
r3
-T
r6
.
When testing the system LSI
1
before shipment out of the factory, the reference voltage V
r
output from the measuring output pad P is measured by a measuring apparatus to determine whether or not the reference voltage V
r
is within a predetermined range. If the measured reference voltage V
r
is not in the predetermined range, trimming is carried using the fuses f
01
, f
02
in accordance with the amount offset from the predetermined range. The reference voltage generating circuit
22
generates the reference voltage V
r
in accordance with the level based on the combination of the fuses f
01
, f
02
that undergo or do not undergo trimming, or in accordance with the predetermined voltage value. Such trimming is conducted on each of the memory macros
2
Ishida Yoshiyuki
Itoh Eisaku
Ogawa Yasushige
Armstrong, Westerman, Hattori, McLeland & Naughton, LLP.
Fujitsu Limited
Nelms David
Tran M.
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