Coded data generation or conversion – Converter calibration or testing – Trimming control circuits
Reexamination Certificate
2000-02-24
2001-10-23
JeanPierre, Peguy (Department: 2819)
Coded data generation or conversion
Converter calibration or testing
Trimming control circuits
C341S144000, C341S155000
Reexamination Certificate
active
06307491
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to trimming (i.e., adjustment) of electronic circuits to improve their performance parameters.
2. Description of the Related Art
Elements of electronic circuits are often trimmed during manufacture and test to enhance the circuit's performance parameters. When the performance parameters must meet rigorous specifications, analysis algorithms are often used to determine circuit errors and the trimming required to reduce these errors.
It would be advantageous to be able to temporarily effect an experimental trim and have the ability to “untrim” the circuit if necessary. If, in contrast, “hard-trimming” is the only available option, then an improperly trimmed circuit is ruined and the trimming operator must proceed to another part which may have significantly different errors that require adjustment of the analysis algorithm. If an option were available for addressable and reversible trimming, the operator could adjust the analysis algorithm and repeatedly “re-trim” the same part.
SUMMARY OF THE INVENTION
The present invention is directed to trim systems and methods that have temporary and permanent operational modes for trimming electronic circuits with set and reset trim signals. The temporary mode permits a circuit's performance parameters to be evaluated when various combinations of set and reset trim signals are applied. The permanent mode is then used to permanently apply a preferred combination of set and reset trim signals to the circuit.
These objectives are realized with latch systems that include:
a) a latch that generates set and reset trim signals in respective response to set and reset latch signals;
b) a reset driver that applies the reset latch signal to the latch;
c) temporary-set driver which removes the reset latch signal from the latch in response to a mode-select signal and which applies the set latch signal to the latch in response to a state-select signal; and
d) a permanent-set driver which includes a trimmable link and which responds to the trimming of the link by removing the reset latch signal from the latch and applying the set latch signal to the latch.
These latch systems facilitate the use of latch methods that include the steps of:
a) temporarily latching each of a plurality of trim signals in a an experimental combination of set and reset trim states;
b) assessing the response of the circuit's performance parameters to the experimental combination;
c) repeating steps a) and b) to find a preferred combination of set and reset trim states; and
d) permanently latching the trim signals in the preferred combination.
The novel features of the invention are set forth with particularity in the appended claims. The invention will be best understood from the following description when read in conjunction with the accompanying drawings.
REFERENCES:
patent: 5596322 (1997-01-01), Marsh et al.
patent: 5635934 (1997-06-01), Brown
patent: 5642116 (1997-06-01), Gersbach et al.
patent: 5760720 (1998-06-01), Nolan et al.
patent: 5933370 (1999-08-01), Holzman et al.
patent: 5973631 (1999-10-01), McMullen
Sheingold, David H. (edited by),Analog-Digital Conversion Handbook, Prentice Hall, Englewood Cliffs, New Jersey, 1986, pp. 533-541.
Moreland Carl W.
Stop Russel G.
Analog Devices Inc.
Jean-Pierre Peguy
Koppel & Jacobs
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